Search

Thomas M Sember

Examiner (ID: 1518, Phone: (571)272-2381 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875, 2885, 3406, 3621, 2215
Total Applications
2896
Issued Applications
2391
Pending Applications
127
Abandoned Applications
377

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5401821 [patent_doc_number] => 20090237134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'MINIMIZING CLOCK UNCERTAINTY ON CLOCK DISTRIBUTION NETWORKS USING A MULTI-LEVEL DE-SKEWING TECHNIQUE' [patent_app_type] => utility [patent_app_number] => 12/051834 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4509 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20090237134.pdf [firstpage_image] =>[orig_patent_app_number] => 12051834 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051834
Minimizing clock uncertainty on clock distribution networks using a multi-level de-skewing technique Mar 18, 2008 Issued
Array ( [id] => 4631903 [patent_doc_number] => 08010813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Structure for system for extending the useful life of another system' [patent_app_type] => utility [patent_app_number] => 12/051001 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6671 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/010/08010813.pdf [firstpage_image] =>[orig_patent_app_number] => 12051001 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051001
Structure for system for extending the useful life of another system Mar 18, 2008 Issued
Array ( [id] => 5405649 [patent_doc_number] => 20090240964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'Method and apparatus for holistic power management to dynamically and automatically turn servers, network equipment and facility components on and off inside and across multiple data centers based on a variety of parameters without violating existing service levels' [patent_app_type] => utility [patent_app_number] => 12/051833 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4887 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20090240964.pdf [firstpage_image] =>[orig_patent_app_number] => 12051833 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051833
Method and apparatus for holistic power management to dynamically and automatically turn servers, network equipment and facility components on and off inside and across multiple data centers based on a variety of parameters without violating existing service levels Mar 18, 2008 Issued
Array ( [id] => 7495141 [patent_doc_number] => 08032778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Clock distribution apparatus, systems, and methods' [patent_app_type] => utility [patent_app_number] => 12/051745 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5263 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/032/08032778.pdf [firstpage_image] =>[orig_patent_app_number] => 12051745 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051745
Clock distribution apparatus, systems, and methods Mar 18, 2008 Issued
Array ( [id] => 4641992 [patent_doc_number] => 08020027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-13 [patent_title] => 'Timing control in a specialized processing block' [patent_app_type] => utility [patent_app_number] => 12/049560 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4072 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/020/08020027.pdf [firstpage_image] =>[orig_patent_app_number] => 12049560 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/049560
Timing control in a specialized processing block Mar 16, 2008 Issued
Array ( [id] => 4522726 [patent_doc_number] => 07917796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Method and apparatus for the generation and control of clock signals' [patent_app_type] => utility [patent_app_number] => 12/069266 [patent_app_country] => US [patent_app_date] => 2008-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7395 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/917/07917796.pdf [firstpage_image] =>[orig_patent_app_number] => 12069266 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/069266
Method and apparatus for the generation and control of clock signals Feb 7, 2008 Issued
Array ( [id] => 9218451 [patent_doc_number] => 08631261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Context state management for processor feature sets' [patent_app_type] => utility [patent_app_number] => 11/967303 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2844 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11967303 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967303
Context state management for processor feature sets Dec 30, 2007 Issued
Array ( [id] => 5432794 [patent_doc_number] => 20090167380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'System and method for reducing EME emissions in digital desynchronized circuits' [patent_app_type] => utility [patent_app_number] => 12/003468 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5068 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20090167380.pdf [firstpage_image] =>[orig_patent_app_number] => 12003468 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/003468
System and method for reducing EME emissions in digital desynchronized circuits Dec 25, 2007 Abandoned
Array ( [id] => 4881078 [patent_doc_number] => 20080154461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Apparatus, system and method for allowing prescribed components in the system to be started with minimal delay' [patent_app_type] => utility [patent_app_number] => 12/002935 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5408 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20080154461.pdf [firstpage_image] =>[orig_patent_app_number] => 12002935 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/002935
Apparatus, system and method for allowing prescribed components in the system to be started with minimal delay Dec 18, 2007 Issued
Array ( [id] => 4700225 [patent_doc_number] => 20080222409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Memory access system and memory access method thereof' [patent_app_type] => utility [patent_app_number] => 12/000591 [patent_app_country] => US [patent_app_date] => 2007-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3281 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222409.pdf [firstpage_image] =>[orig_patent_app_number] => 12000591 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000591
Memory access system and memory access method thereof Dec 13, 2007 Issued
Array ( [id] => 4869032 [patent_doc_number] => 20080148091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Signal bus, multilevel input interface and information processor' [patent_app_type] => utility [patent_app_number] => 12/001911 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5306 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148091.pdf [firstpage_image] =>[orig_patent_app_number] => 12001911 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/001911
Signal bus, multilevel input interface and information processor Dec 12, 2007 Issued
Array ( [id] => 5548200 [patent_doc_number] => 20090158077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Circuit and method for generation of duty cycle independent core clock' [patent_app_type] => utility [patent_app_number] => 12/001730 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4352 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158077.pdf [firstpage_image] =>[orig_patent_app_number] => 12001730 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/001730
Circuit and method for generation of duty cycle independent core clock Dec 11, 2007 Issued
Array ( [id] => 5548201 [patent_doc_number] => 20090158078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof' [patent_app_type] => utility [patent_app_number] => 12/000413 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158078.pdf [firstpage_image] =>[orig_patent_app_number] => 12000413 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000413
Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof Dec 11, 2007 Issued
Array ( [id] => 7529965 [patent_doc_number] => 08046571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-25 [patent_title] => 'System-on-a-chip (SoC) security using one-time programmable memories' [patent_app_type] => utility [patent_app_number] => 12/001107 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6764 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/046/08046571.pdf [firstpage_image] =>[orig_patent_app_number] => 12001107 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/001107
System-on-a-chip (SoC) security using one-time programmable memories Dec 9, 2007 Issued
Array ( [id] => 5280665 [patent_doc_number] => 20090132797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Methods, Media and Apparatus for Booting Diskless Systems' [patent_app_type] => utility [patent_app_number] => 11/944018 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20090132797.pdf [firstpage_image] =>[orig_patent_app_number] => 11944018 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/944018
Methods, media and apparatus for booting diskless systems Nov 20, 2007 Issued
Array ( [id] => 4636956 [patent_doc_number] => 08015420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'System and method for power management of a storage enclosure' [patent_app_type] => utility [patent_app_number] => 11/944026 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4682 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/015/08015420.pdf [firstpage_image] =>[orig_patent_app_number] => 11944026 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/944026
System and method for power management of a storage enclosure Nov 20, 2007 Issued
Array ( [id] => 5280667 [patent_doc_number] => 20090132799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Systems and Methods for Configuring Out-of-Band Bios Settings' [patent_app_type] => utility [patent_app_number] => 11/943110 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20090132799.pdf [firstpage_image] =>[orig_patent_app_number] => 11943110 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943110
Systems and methods for configuring out-of-band bios settings Nov 19, 2007 Issued
Array ( [id] => 4810924 [patent_doc_number] => 20080191555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'COMPUTER AND POWER SUPPLY METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/942181 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191555.pdf [firstpage_image] =>[orig_patent_app_number] => 11942181 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942181
Computer and power supply method thereof Nov 18, 2007 Issued
Array ( [id] => 4830010 [patent_doc_number] => 20080126775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'ELECTRONIC APPARATUS INCORPORATING A PLURALITY OF MICROPROCESSOR UNITS' [patent_app_type] => utility [patent_app_number] => 11/942524 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3420 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126775.pdf [firstpage_image] =>[orig_patent_app_number] => 11942524 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942524
Electronic apparatus incorporating a plurality of microprocessor units for use in initializing data Nov 18, 2007 Issued
Array ( [id] => 4792475 [patent_doc_number] => 20080293449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'METHOD AND SYSTEM FOR PARTITIONING A DEVICE INTO DOMAINS TO OPTIMIZE POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 11/933851 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6734 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20080293449.pdf [firstpage_image] =>[orig_patent_app_number] => 11933851 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933851
METHOD AND SYSTEM FOR PARTITIONING A DEVICE INTO DOMAINS TO OPTIMIZE POWER CONSUMPTION Oct 31, 2007 Abandoned
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