Search

Thomas N. Moulis

Examiner (ID: 16587, Phone: (571)272-4852 , Office: P/3747 )

Most Active Art Unit
3747
Art Unit(s)
3402, 3747
Total Applications
2821
Issued Applications
2594
Pending Applications
48
Abandoned Applications
186

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17507424 [patent_doc_number] => 20220100527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SUPPORTING INSTRUCTION SET ARCHITECTURE COMPONENTS ACROSS RELEASES [patent_app_type] => utility [patent_app_number] => 17/037194 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037194
Supporting instruction set architecture components across releases Sep 28, 2020 Issued
Array ( [id] => 18130134 [patent_doc_number] => 11556342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-17 [patent_title] => Configurable delay insertion in compiled instructions [patent_app_type] => utility [patent_app_number] => 17/031495 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11940 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031495 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031495
Configurable delay insertion in compiled instructions Sep 23, 2020 Issued
Array ( [id] => 17817354 [patent_doc_number] => 11422968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Methods, devices and systems for high speed serial bus transactions [patent_app_type] => utility [patent_app_number] => 17/030664 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 37 [patent_no_of_words] => 10949 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030664
Methods, devices and systems for high speed serial bus transactions Sep 23, 2020 Issued
Array ( [id] => 16577471 [patent_doc_number] => 20210011872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => MULTICORE BUS ARCHITECTURE WITH NON-BLOCKING HIGH PERFORMANCE TRANSACTION CREDIT SYSTEM [patent_app_type] => utility [patent_app_number] => 17/030518 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030518 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030518
Multicore bus architecture with non-blocking high performance transaction credit system Sep 23, 2020 Issued
Array ( [id] => 16722167 [patent_doc_number] => 20210089314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => PATH PREDICTION METHOD USED FOR INSTRUCTION CACHE, ACCESS CONTROL UNIT, AND INSTRCUTION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/017047 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017047 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017047
Path prediction method used for instruction cache, access control unit, and instruction processing apparatus Sep 9, 2020 Issued
Array ( [id] => 17276646 [patent_doc_number] => 20210382844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => OIS CIRCUIT, OIS DATA SHARING DEVICE, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/015402 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17015402 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/015402
OIS circuit, OIS data sharing device, and operating method thereof Sep 8, 2020 Issued
Array ( [id] => 16527243 [patent_doc_number] => 20200401323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => STREAMING DATA SERVICE WITH ISOLATED READ CHANNELS [patent_app_type] => utility [patent_app_number] => 17/013441 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 46094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17013441 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/013441
Streaming data service with isolated read channels Sep 3, 2020 Issued
Array ( [id] => 17802135 [patent_doc_number] => 11416436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Device with a fountain code decoding unit for reconstructing a configuration data record [patent_app_type] => utility [patent_app_number] => 17/013427 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17013427 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/013427
Device with a fountain code decoding unit for reconstructing a configuration data record Sep 3, 2020 Issued
Array ( [id] => 17744317 [patent_doc_number] => 11392384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Methods of breaking down coarse-grained tasks for fine-grained task re-scheduling [patent_app_type] => utility [patent_app_number] => 17/013384 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17013384 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/013384
Methods of breaking down coarse-grained tasks for fine-grained task re-scheduling Sep 3, 2020 Issued
Array ( [id] => 17999695 [patent_doc_number] => 11500803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Programmable slave circuit on a communication bus [patent_app_type] => utility [patent_app_number] => 17/009064 [patent_app_country] => US [patent_app_date] => 2020-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4931 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17009064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/009064
Programmable slave circuit on a communication bus Aug 31, 2020 Issued
Array ( [id] => 17408875 [patent_doc_number] => 11249757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-15 [patent_title] => Handling and fusing load instructions in a processor [patent_app_type] => utility [patent_app_number] => 16/993552 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10080 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16993552 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/993552
Handling and fusing load instructions in a processor Aug 13, 2020 Issued
Array ( [id] => 19138631 [patent_doc_number] => 11973616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => ETHERCAT bus system including an ETHERCAT bus master and ETHERCAT bus station [patent_app_type] => utility [patent_app_number] => 17/641377 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1516 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17641377 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/641377
ETHERCAT bus system including an ETHERCAT bus master and ETHERCAT bus station Aug 5, 2020 Issued
Array ( [id] => 18934445 [patent_doc_number] => 11886879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Processor, processor operation method and electronic device comprising same for selective instruction execution based on operand address [patent_app_type] => utility [patent_app_number] => 17/630892 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7871 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17630892 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/630892
Processor, processor operation method and electronic device comprising same for selective instruction execution based on operand address Aug 5, 2020 Issued
Array ( [id] => 16616326 [patent_doc_number] => 20210034979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => NEURAL NETWORK DATA COMPUTATION USING MIXED-PRECISION [patent_app_type] => utility [patent_app_number] => 16/985307 [patent_app_country] => US [patent_app_date] => 2020-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16985307 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/985307
Neural network data computation using mixed-precision Aug 4, 2020 Issued
Array ( [id] => 17499366 [patent_doc_number] => 11288072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Multi-threaded processor with thread granularity [patent_app_type] => utility [patent_app_number] => 16/945936 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5018 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945936 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/945936
Multi-threaded processor with thread granularity Aug 2, 2020 Issued
Array ( [id] => 18154793 [patent_doc_number] => 11567771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Method and apparatus for back end gather/scatter memory coalescing [patent_app_type] => utility [patent_app_number] => 16/944146 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6354 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16944146 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/944146
Method and apparatus for back end gather/scatter memory coalescing Jul 29, 2020 Issued
Array ( [id] => 16438948 [patent_doc_number] => 20200356274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => METHOD TO ADDRESS MISALIGNED HOLES AND WRITES TO END OF FILES WHILE PERFORMING QUICK RECONCILE OPERATION DURING SYNCHRONOUS FILESYSTEM REPLICATION [patent_app_type] => utility [patent_app_number] => 16/940462 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940462 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940462
Serializing execution of replication operations Jul 27, 2020 Issued
Array ( [id] => 16600261 [patent_doc_number] => 20210026792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => METHOD FOR DATA COMMUNICATION BETWEEN FIELDBUS DEVICES AND A CONTROL DESK OF AN AUTOMATION SYSTEM, AND AUTOMATION SYSTEM [patent_app_type] => utility [patent_app_number] => 16/938691 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 465 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16938691 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/938691
Method for data communication between fieldbus devices and a control desk of an automation system, and automation system Jul 23, 2020 Issued
Array ( [id] => 18136118 [patent_doc_number] => 11561796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Linked miss-to-miss instruction prefetcher [patent_app_type] => utility [patent_app_number] => 16/929208 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6504 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929208 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929208
Linked miss-to-miss instruction prefetcher Jul 14, 2020 Issued
Array ( [id] => 16910334 [patent_doc_number] => 11042373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Computation engine that operates in matrix and vector modes [patent_app_type] => utility [patent_app_number] => 16/928752 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928752 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/928752
Computation engine that operates in matrix and vector modes Jul 13, 2020 Issued
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