Search

Thomas N. Moulis

Examiner (ID: 16587, Phone: (571)272-4852 , Office: P/3747 )

Most Active Art Unit
3747
Art Unit(s)
3402, 3747
Total Applications
2821
Issued Applications
2594
Pending Applications
48
Abandoned Applications
186

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17469141 [patent_doc_number] => 11275618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Method, device and medium for allocating resource based on type of PCI device [patent_app_type] => utility [patent_app_number] => 16/475111 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5206 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16475111 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/475111
Method, device and medium for allocating resource based on type of PCI device Dec 25, 2018 Issued
Array ( [id] => 16446956 [patent_doc_number] => 10838885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Method for supporting erasure code data protection with embedded PCIE switch inside FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/226629 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 27220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226629 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226629
Method for supporting erasure code data protection with embedded PCIE switch inside FPGA+SSD Dec 18, 2018 Issued
Array ( [id] => 16764179 [patent_doc_number] => 20210109760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/965074 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16965074 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/965074
Processing system with a main processor pipeline and a co-processor pipeline Dec 16, 2018 Issued
Array ( [id] => 15757693 [patent_doc_number] => 10620958 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-14 [patent_title] => Crossbar between clients and a cache [patent_app_type] => utility [patent_app_number] => 16/208010 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208010 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/208010
Crossbar between clients and a cache Dec 2, 2018 Issued
Array ( [id] => 15820859 [patent_doc_number] => 10635609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Method for supporting erasure code data protection with embedded PCIE switch inside FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/207080 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 24259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16207080 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/207080
Method for supporting erasure code data protection with embedded PCIE switch inside FPGA+SSD Nov 29, 2018 Issued
Array ( [id] => 14443827 [patent_doc_number] => 20190179787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => DEVICE AND METHOD FOR CONTROLLING PRIORITY-BASED VEHICLE MULTI-MASTER MODULE [patent_app_type] => utility [patent_app_number] => 16/204971 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/204971
Device and method for controlling priority-based vehicle multi-master module Nov 28, 2018 Issued
Array ( [id] => 14798721 [patent_doc_number] => 10402365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Data lane validation procedure for multilane protocols [patent_app_type] => utility [patent_app_number] => 16/201369 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 17439 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/201369
Data lane validation procedure for multilane protocols Nov 26, 2018 Issued
Array ( [id] => 14347271 [patent_doc_number] => 20190155608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => FAST PIPELINE RESTART IN PROCESSOR WITH DECOUPLED FETCHER [patent_app_type] => utility [patent_app_number] => 16/193935 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16193935 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/193935
FAST PIPELINE RESTART IN PROCESSOR WITH DECOUPLED FETCHER Nov 15, 2018 Abandoned
Array ( [id] => 16232590 [patent_doc_number] => 10740140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Flush-recovery bandwidth in a processor [patent_app_type] => utility [patent_app_number] => 16/193260 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16193260 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/193260
Flush-recovery bandwidth in a processor Nov 15, 2018 Issued
Array ( [id] => 16667072 [patent_doc_number] => 10936318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Tagged indirect branch predictor (TIP) [patent_app_type] => utility [patent_app_number] => 16/190309 [patent_app_country] => US [patent_app_date] => 2018-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6345 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16190309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/190309
Tagged indirect branch predictor (TIP) Nov 13, 2018 Issued
Array ( [id] => 15902895 [patent_doc_number] => 20200150967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => MISPREDICTION OF PREDICTED TAKEN BRANCHES IN A DATA PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/185073 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16185073 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/185073
Misprediction of predicted taken branches in a data processing apparatus Nov 8, 2018 Issued
Array ( [id] => 18046727 [patent_doc_number] => 11520681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => System log collection method [patent_app_type] => utility [patent_app_number] => 16/645574 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3506 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16645574 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/645574
System log collection method Oct 30, 2018 Issued
Array ( [id] => 15638329 [patent_doc_number] => 10592158 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-17 [patent_title] => Method and system for transferring data to a target storage system using perfect hash functions [patent_app_type] => utility [patent_app_number] => 16/174497 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5751 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16174497 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/174497
Method and system for transferring data to a target storage system using perfect hash functions Oct 29, 2018 Issued
Array ( [id] => 17309134 [patent_doc_number] => 11210245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Data transmission techniques between systems having different communication speeds [patent_app_type] => utility [patent_app_number] => 16/155305 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12126 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 481 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16155305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/155305
Data transmission techniques between systems having different communication speeds Oct 8, 2018 Issued
Array ( [id] => 14966735 [patent_doc_number] => 20190310846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => COMPRESSED INSTRUCTION FORMAT [patent_app_type] => utility [patent_app_number] => 16/155028 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16155028 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/155028
Compressed instruction format Oct 8, 2018 Issued
Array ( [id] => 15789289 [patent_doc_number] => 10628369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Header improvements in packets accessing contiguous addresses [patent_app_type] => utility [patent_app_number] => 16/153200 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 7522 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16153200 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/153200
Header improvements in packets accessing contiguous addresses Oct 4, 2018 Issued
Array ( [id] => 15700827 [patent_doc_number] => 10606589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Vector checksum instruction [patent_app_type] => utility [patent_app_number] => 16/148493 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 18060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148493 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148493
Vector checksum instruction Sep 30, 2018 Issued
Array ( [id] => 17024216 [patent_doc_number] => 20210248087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => DATA STORED OR FREE SPACE BASED FIFO BUFFER [patent_app_type] => utility [patent_app_number] => 17/054762 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17054762 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/054762
Data stored or free space based FIFO buffer Sep 26, 2018 Issued
Array ( [id] => 15670735 [patent_doc_number] => 10599598 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-24 [patent_title] => PCIe write request acknowledgment [patent_app_type] => utility [patent_app_number] => 16/134499 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8727 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16134499 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/134499
PCIe write request acknowledgment Sep 17, 2018 Issued
Array ( [id] => 17861581 [patent_doc_number] => 11442738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Method for executing a machine code of a secure function [patent_app_type] => utility [patent_app_number] => 16/643906 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 11882 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16643906 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/643906
Method for executing a machine code of a secure function Sep 13, 2018 Issued
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