Search

Thomas N. Moulis

Examiner (ID: 16587, Phone: (571)272-4852 , Office: P/3747 )

Most Active Art Unit
3747
Art Unit(s)
3402, 3747
Total Applications
2821
Issued Applications
2594
Pending Applications
48
Abandoned Applications
186

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11823758 [patent_doc_number] => 20170212695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'APPARATUSES AND METHODS FOR ENCODING AND DECODING OF SIGNAL LINES FOR MULTI-LEVEL COMMUNICATION ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 15/004777 [patent_app_country] => US [patent_app_date] => 2016-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12207 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15004777 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/004777
Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures Jan 21, 2016 Issued
Array ( [id] => 15137153 [patent_doc_number] => 10482044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Computer, device control system, and device control method for direct memory access [patent_app_type] => utility [patent_app_number] => 15/541393 [patent_app_country] => US [patent_app_date] => 2016-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6651 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15541393 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/541393
Computer, device control system, and device control method for direct memory access Jan 14, 2016 Issued
Array ( [id] => 13710831 [patent_doc_number] => 20170366370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => FUNCTION CONNECTION UNIT COMPRISING A PARAMETER MEMORY [patent_app_type] => utility [patent_app_number] => 15/535979 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15535979 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/535979
Function connection unit comprising a parameter memory Dec 14, 2015 Issued
Array ( [id] => 11306684 [patent_doc_number] => 09514083 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-06 [patent_title] => 'Topology specific replicated bus unit addressing in a data processing system' [patent_app_type] => utility [patent_app_number] => 14/960507 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6301 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14960507 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/960507
Topology specific replicated bus unit addressing in a data processing system Dec 6, 2015 Issued
Array ( [id] => 10731604 [patent_doc_number] => 20160077754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SYSTEM AND METHOD FOR DIVIDING AND SYNCHRONIZING A PROCESSING TASK\nACROSS MULTIPLE PROCESSING ELEMENTS/PROCESSORS IN HARDWARE' [patent_app_type] => utility [patent_app_number] => 14/952320 [patent_app_country] => US [patent_app_date] => 2015-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952320 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/952320
System and method for dividing and synchronizing a processing task across multiple processing elements/processors in hardware Nov 24, 2015 Issued
Array ( [id] => 11384932 [patent_doc_number] => 20170010988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'ACTIVATION METHOD OF A UNIVERSAL SERIAL BUS COMPATIBLE FLASH DEVICE AND RELATED UNIVERSAL SERIAL BUS COMPATIBLE FLASH DEVICE' [patent_app_type] => utility [patent_app_number] => 14/920890 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2954 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920890 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920890
ACTIVATION METHOD OF A UNIVERSAL SERIAL BUS COMPATIBLE FLASH DEVICE AND RELATED UNIVERSAL SERIAL BUS COMPATIBLE FLASH DEVICE Oct 22, 2015 Abandoned
Array ( [id] => 13172121 [patent_doc_number] => 10102177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Serial communication system, communication control unit, and electronic device for finding and assigning unused addresses [patent_app_type] => utility [patent_app_number] => 14/919961 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10852 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14919961 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/919961
Serial communication system, communication control unit, and electronic device for finding and assigning unused addresses Oct 21, 2015 Issued
Array ( [id] => 10771121 [patent_doc_number] => 20160117277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'COLLABORATIVE HARDWARE INTERACTION BY MULTIPLE ENTITIES USING A SHARED QUEUE' [patent_app_type] => utility [patent_app_number] => 14/918599 [patent_app_country] => US [patent_app_date] => 2015-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5868 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918599 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/918599
Collaborative hardware interaction by multiple entities using a shared queue Oct 20, 2015 Issued
Array ( [id] => 11889951 [patent_doc_number] => 09760513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Low latency efficient sharing of resources in multi-server ecosystems' [patent_app_type] => utility [patent_app_number] => 14/861866 [patent_app_country] => US [patent_app_date] => 2015-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7679 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14861866 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/861866
Low latency efficient sharing of resources in multi-server ecosystems Sep 21, 2015 Issued
Array ( [id] => 13069193 [patent_doc_number] => 10055376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-21 [patent_title] => Serial peripheral interface system with slave expander [patent_app_type] => utility [patent_app_number] => 14/860625 [patent_app_country] => US [patent_app_date] => 2015-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 14863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14860625 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/860625
Serial peripheral interface system with slave expander Sep 20, 2015 Issued
Array ( [id] => 11780686 [patent_doc_number] => 09389867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Speculative finish of instruction execution in a processor core' [patent_app_type] => utility [patent_app_number] => 14/840997 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 11089 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14840997 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/840997
Speculative finish of instruction execution in a processor core Aug 30, 2015 Issued
Array ( [id] => 12194705 [patent_doc_number] => 09898436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Data transmission system and transmission method thereof including connection and orientation detection' [patent_app_type] => utility [patent_app_number] => 14/810938 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8465 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 413 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810938 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810938
Data transmission system and transmission method thereof including connection and orientation detection Jul 27, 2015 Issued
Array ( [id] => 12966451 [patent_doc_number] => 09875045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Regular expression matching with back-references using backtracking [patent_app_type] => utility [patent_app_number] => 14/809617 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6237 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809617 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/809617
Regular expression matching with back-references using backtracking Jul 26, 2015 Issued
Array ( [id] => 10439213 [patent_doc_number] => 20150324225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM SELECTIVELY OPERATING AS ONE OF A BIG ENDIAN OR LITTLE ENDIAN SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/802836 [patent_app_country] => US [patent_app_date] => 2015-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5993 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14802836 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/802836
Semiconductor device and data processing system selectively operating as one of a big endian or little endian system Jul 16, 2015 Issued
Array ( [id] => 11272666 [patent_doc_number] => 20160335213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'MOTHERBOARD WITH MULTIPLE INTERFACES' [patent_app_type] => utility [patent_app_number] => 14/794978 [patent_app_country] => US [patent_app_date] => 2015-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1042 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794978 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794978
MOTHERBOARD WITH MULTIPLE INTERFACES Jul 8, 2015 Abandoned
Array ( [id] => 13767565 [patent_doc_number] => 10176126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-08 [patent_title] => Methods, systems, and computer program product for a PCI implementation handling multiple packets [patent_app_type] => utility [patent_app_number] => 14/754508 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 11051 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14754508 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/754508
Methods, systems, and computer program product for a PCI implementation handling multiple packets Jun 28, 2015 Issued
Array ( [id] => 12332061 [patent_doc_number] => 09946681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-17 [patent_title] => Host configured multi serial interface device [patent_app_type] => utility [patent_app_number] => 14/753944 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4552 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14753944 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/753944
Host configured multi serial interface device Jun 28, 2015 Issued
Array ( [id] => 13679787 [patent_doc_number] => 20160378630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => PORT MONITORING SYSTEM [patent_app_type] => utility [patent_app_number] => 14/750764 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750764 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750764
PORT MONITORING SYSTEM Jun 24, 2015 Abandoned
Array ( [id] => 11686579 [patent_doc_number] => 09684626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Wireless transmission and video integrated apparatus' [patent_app_type] => utility [patent_app_number] => 14/747337 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4774 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14747337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/747337
Wireless transmission and video integrated apparatus Jun 22, 2015 Issued
Array ( [id] => 12352491 [patent_doc_number] => 09953006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Lock-free processing of stateless protocols over RDMA [patent_app_type] => utility [patent_app_number] => 14/747231 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6205 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14747231 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/747231
Lock-free processing of stateless protocols over RDMA Jun 22, 2015 Issued
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