Search

Thomas N. Moulis

Examiner (ID: 16587, Phone: (571)272-4852 , Office: P/3747 )

Most Active Art Unit
3747
Art Unit(s)
3402, 3747
Total Applications
2821
Issued Applications
2594
Pending Applications
48
Abandoned Applications
186

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10292725 [patent_doc_number] => 20150177725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'NUMERICAL CONTROL SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/573363 [patent_app_country] => US [patent_app_date] => 2014-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3407 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14573363 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/573363
Numerical control system Dec 16, 2014 Issued
Array ( [id] => 10301311 [patent_doc_number] => 20150186312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'APPARATUS AND METHOD FOR SENSING OBJECT STATE' [patent_app_type] => utility [patent_app_number] => 14/565685 [patent_app_country] => US [patent_app_date] => 2014-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5195 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14565685 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/565685
APPARATUS AND METHOD FOR SENSING OBJECT STATE Dec 9, 2014 Abandoned
Array ( [id] => 10746239 [patent_doc_number] => 20160092391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'INTERFACE APPARATUS, VEHICLE HAVING THE SAME, AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/566418 [patent_app_country] => US [patent_app_date] => 2014-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6362 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14566418 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/566418
INTERFACE APPARATUS, VEHICLE HAVING THE SAME, AND METHOD OF CONTROLLING THE SAME Dec 9, 2014 Abandoned
Array ( [id] => 10816268 [patent_doc_number] => 20160162429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'SYSTEM AND METHOD FOR NON-UNICAST/DESINTATION LOOKUP FAIL (DLF) LOAD BALANCING' [patent_app_type] => utility [patent_app_number] => 14/565248 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14565248 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/565248
Systems and methods for non-unicast/destination lookup fail (DLF) load balancing Dec 8, 2014 Issued
Array ( [id] => 10258083 [patent_doc_number] => 20150143080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'VECTOR CHECKSUM INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/564155 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18623 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564155 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/564155
Vector checksum instruction Dec 8, 2014 Issued
Array ( [id] => 10210633 [patent_doc_number] => 20150095624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'VECTOR FLOATING POINT TEST DATA CLASS IMMEDIATE INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/561459 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18642 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14561459 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/561459
Vector floating point test data class immediate instruction Dec 4, 2014 Issued
Array ( [id] => 10204206 [patent_doc_number] => 20150089194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'PREDICTIVE FETCHING AND DECODING FOR SELECTED INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/558808 [patent_app_country] => US [patent_app_date] => 2014-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 18485 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14558808 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/558808
Predictive fetching and decoding for selected instructions Dec 2, 2014 Issued
Array ( [id] => 11359050 [patent_doc_number] => 09535703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Predictor data structure for use in pipelined processing' [patent_app_type] => utility [patent_app_number] => 14/559087 [patent_app_country] => US [patent_app_date] => 2014-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 18481 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14559087 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/559087
Predictor data structure for use in pipelined processing Dec 2, 2014 Issued
Array ( [id] => 10204110 [patent_doc_number] => 20150089098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'SYNCHRONOUS NETWORK OF SUPERSPEED AND NON-SUPERSPEED USB DEVICES' [patent_app_type] => utility [patent_app_number] => 14/557150 [patent_app_country] => US [patent_app_date] => 2014-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557150 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/557150
SYNCHRONOUS NETWORK OF SUPERSPEED AND NON-SUPERSPEED USB DEVICES Nov 30, 2014 Abandoned
Array ( [id] => 10644239 [patent_doc_number] => 09361108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Forming instruction groups based on decode time instruction optimization' [patent_app_type] => utility [patent_app_number] => 14/550955 [patent_app_country] => US [patent_app_date] => 2014-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 16171 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14550955 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/550955
Forming instruction groups based on decode time instruction optimization Nov 21, 2014 Issued
Array ( [id] => 10793918 [patent_doc_number] => 20160140076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'APPARATUS FOR TRANSFERRING DATA BETWEEN DEVICES' [patent_app_type] => utility [patent_app_number] => 14/542584 [patent_app_country] => US [patent_app_date] => 2014-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14542584 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/542584
APPARATUS FOR TRANSFERRING DATA BETWEEN DEVICES Nov 14, 2014 Abandoned
Array ( [id] => 10793723 [patent_doc_number] => 20160139880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'Bypass FIFO for Multiple Virtual Channels' [patent_app_type] => utility [patent_app_number] => 14/541917 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8620 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14541917 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/541917
Bypass FIFO for multiple virtual channels Nov 13, 2014 Issued
Array ( [id] => 10793904 [patent_doc_number] => 20160140061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'MANAGING BUFFERED COMMUNICATION BETWEEN CORES' [patent_app_type] => utility [patent_app_number] => 14/542118 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3647 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14542118 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/542118
Managing buffered communication between cores Nov 13, 2014 Issued
Array ( [id] => 10275951 [patent_doc_number] => 20150160948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'FIRMWARE UPDATES DURING LIMITED TIME PERIOD' [patent_app_type] => utility [patent_app_number] => 14/537786 [patent_app_country] => US [patent_app_date] => 2014-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14881 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14537786 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/537786
Firmware updates during limited time period Nov 9, 2014 Issued
Array ( [id] => 12201579 [patent_doc_number] => 09904645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Multicore bus architecture with non-blocking high performance transaction credit system' [patent_app_type] => utility [patent_app_number] => 14/530203 [patent_app_country] => US [patent_app_date] => 2014-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 21250 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530203 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/530203
Multicore bus architecture with non-blocking high performance transaction credit system Oct 30, 2014 Issued
Array ( [id] => 10778731 [patent_doc_number] => 20160124888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'Memory Bus Loading and Conditioning Module' [patent_app_type] => utility [patent_app_number] => 14/530201 [patent_app_country] => US [patent_app_date] => 2014-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3756 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530201 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/530201
Memory Bus Loading and Conditioning Module Oct 30, 2014 Abandoned
Array ( [id] => 11700811 [patent_doc_number] => 09690727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'System internal latency measurements in realtime applications' [patent_app_type] => utility [patent_app_number] => 14/530622 [patent_app_country] => US [patent_app_date] => 2014-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2445 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530622 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/530622
System internal latency measurements in realtime applications Oct 30, 2014 Issued
Array ( [id] => 11577522 [patent_doc_number] => 09632783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Operand conflict resolution for reduced port general purpose register' [patent_app_type] => utility [patent_app_number] => 14/505854 [patent_app_country] => US [patent_app_date] => 2014-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 17251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14505854 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/505854
Operand conflict resolution for reduced port general purpose register Oct 2, 2014 Issued
Array ( [id] => 12413175 [patent_doc_number] => 09971332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Input/output control device, input/output control method, and non-transitory computer-readable medium for selective activation of logical circuits [patent_app_type] => utility [patent_app_number] => 15/501268 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7514 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15501268 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/501268
Input/output control device, input/output control method, and non-transitory computer-readable medium for selective activation of logical circuits Sep 10, 2014 Issued
Array ( [id] => 10976253 [patent_doc_number] => 20140379288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS' [patent_app_type] => utility [patent_app_number] => 14/480238 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17192 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480238 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/480238
Characterization and validation of processor links Sep 7, 2014 Issued
Menu