Thomas N. Moulis

Array ( [id] => 9794552 [patent_doc_number] => 20150006496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'METHOD AND APPARATUS FOR CONTINUED RETIREMENT DURING COMMIT OF A SPECULATIVE REGION OF CODE' [patent_app_type] => utility [patent_app_number] => 13/931860 [patent_app_country] => US [patent_app_date] => 2013-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14028 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9794508 [patent_doc_number] => 20150006452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'METHOD AND APPARATUS FOR STORE DEPENDENCE PREDICTION' [patent_app_type] => utility [patent_app_number] => 13/931872 [patent_app_country] => US [patent_app_date] => 2013-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7145 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9794910 [patent_doc_number] => 20150006855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'PREDICTIVE FETCHING AND DECODING FOR SELECTED INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/931656 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 18469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9794908 [patent_doc_number] => 20150006852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'FORMING INSTRUCTION GROUPS BASED ON DECODE TIME INSTRUCTION OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 13/931698 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 16155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14034381 [patent_doc_number] => 10228941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register [patent_app_type] => utility [patent_app_number] => 13/931047 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 13605 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9794918 [patent_doc_number] => 20150006862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'PREDICTOR DATA STRUCTURE FOR USE IN PIPELINED PROCESSING' [patent_app_type] => utility [patent_app_number] => 13/931671 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 18468 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11563596 [patent_doc_number] => 09626184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Processors, methods, systems, and instructions to transcode variable length code points of unicode characters' [patent_app_type] => utility [patent_app_number] => 13/931727 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 28137 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11764271 [patent_doc_number] => 09372695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Optimization of instruction groups across group boundaries' [patent_app_type] => utility [patent_app_number] => 13/931680 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 17386 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9213832 [patent_doc_number] => 20140013009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM SELECTIVELY OPERATING AS ONE OF A BIG ENDIAN OR LITTLE ENDIAN SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/922232 [patent_app_country] => US [patent_app_date] => 2013-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5962 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13922232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10158346 [patent_doc_number] => 09190129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Continuous tuning of preamble release timing in a double data-rate memory device interface' [patent_app_type] => utility [patent_app_number] => 13/906610 [patent_app_country] => US [patent_app_date] => 2013-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 8539 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13906610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12966943 [patent_doc_number] => 09875209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation [patent_app_type] => utility [patent_app_number] => 13/887846 [patent_app_country] => US [patent_app_date] => 2013-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9180 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13887846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11577531 [patent_doc_number] => 09632793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Method and device for aborting transactions, related system and computer program product' [patent_app_type] => utility [patent_app_number] => 13/888062 [patent_app_country] => US [patent_app_date] => 2013-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6714 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13888062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10556177 [patent_doc_number] => 09280377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Application with multiple operation modes' [patent_app_type] => utility [patent_app_number] => 13/886889 [patent_app_country] => US [patent_app_date] => 2013-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 15126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13886889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9834274 [patent_doc_number] => 08943103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Improvements to query execution in a parallel elastic database management system' [patent_app_type] => utility [patent_app_number] => 13/874628 [patent_app_country] => US [patent_app_date] => 2013-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 16249 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13874628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10907490 [patent_doc_number] => 20140310504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'Systems and Methods for Flag Tracking in Move Elimination Operations' [patent_app_type] => utility [patent_app_number] => 13/861009 [patent_app_country] => US [patent_app_date] => 2013-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13861009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10616555 [patent_doc_number] => 09335999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Allocating store queue entries to store instructions for early store-to-load forwarding' [patent_app_type] => utility [patent_app_number] => 13/861083 [patent_app_country] => US [patent_app_date] => 2013-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7407 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13861083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9137201 [patent_doc_number] => 20130297916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/859200 [patent_app_country] => US [patent_app_date] => 2013-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8471 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13859200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11213700 [patent_doc_number] => 09442735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-13 [patent_title] => 'Method and apparatus for processing speculative, out-of-order memory access instructions' [patent_app_type] => utility [patent_app_number] => 13/856653 [patent_app_country] => US [patent_app_date] => 2013-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13856653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10616554 [patent_doc_number] => 09335998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Multi-core processor system, monitoring control method, and computer product' [patent_app_type] => utility [patent_app_number] => 13/856934 [patent_app_country] => US [patent_app_date] => 2013-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11045 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13856934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9774332 [patent_doc_number] => 20140297996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'MULTIPLE HASH TABLE INDEXING' [patent_app_type] => utility [patent_app_number] => 13/854171 [patent_app_country] => US [patent_app_date] => 2013-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13854171 [rel_patent_id] =>[rel_patent_doc_number] =>)