
Thomas N. Moulis
Examiner (ID: 16587, Phone: (571)272-4852 , Office: P/3747 )
| Most Active Art Unit | 3747 |
| Art Unit(s) | 3402, 3747 |
| Total Applications | 2821 |
| Issued Applications | 2594 |
| Pending Applications | 48 |
| Abandoned Applications | 186 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18339861
[patent_doc_number] => 20230131810
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-27
[patent_title] => CURRENT VARIATION SLOPE CONTROL METHOD FOR MULTI-CORE PROCESSOR, CONTROL DEVICE AND MEDIUM
[patent_app_type] => utility
[patent_app_number] => 17/958445
[patent_app_country] => US
[patent_app_date] => 2022-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6079
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958445
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/958445 | Current variation slope control method for multi-core processor, control device and medium | Oct 2, 2022 | Issued |
Array
(
[id] => 19243761
[patent_doc_number] => 12014206
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-18
[patent_title] => Pipeline arbitration
[patent_app_type] => utility
[patent_app_number] => 17/958725
[patent_app_country] => US
[patent_app_date] => 2022-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 17667
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958725
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/958725 | Pipeline arbitration | Oct 2, 2022 | Issued |
Array
(
[id] => 18873003
[patent_doc_number] => 11860810
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-02
[patent_title] => Configurable logic platform
[patent_app_type] => utility
[patent_app_number] => 17/952144
[patent_app_country] => US
[patent_app_date] => 2022-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 15770
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952144
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/952144 | Configurable logic platform | Sep 22, 2022 | Issued |
Array
(
[id] => 18973799
[patent_doc_number] => 20240053891
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-15
[patent_title] => Chipset Attached Random Access Memory
[patent_app_type] => utility
[patent_app_number] => 17/887245
[patent_app_country] => US
[patent_app_date] => 2022-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6942
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887245
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/887245 | Chipset attached random access memory | Aug 11, 2022 | Issued |
Array
(
[id] => 18060125
[patent_doc_number] => 20220391211
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-08
[patent_title] => EMBEDDED COMPUTATION INSTRUCTION PERFORMANCE PROFILING
[patent_app_type] => utility
[patent_app_number] => 17/819605
[patent_app_country] => US
[patent_app_date] => 2022-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3591
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819605
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/819605 | Embedded computation instruction performance profiling | Aug 11, 2022 | Issued |
Array
(
[id] => 19493487
[patent_doc_number] => 12112204
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-08
[patent_title] => Modular accelerator function unit (AFU) design, discovery, and reuse
[patent_app_type] => utility
[patent_app_number] => 17/884244
[patent_app_country] => US
[patent_app_date] => 2022-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 13290
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884244
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/884244 | Modular accelerator function unit (AFU) design, discovery, and reuse | Aug 8, 2022 | Issued |
Array
(
[id] => 19107782
[patent_doc_number] => 11960892
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-16
[patent_title] => Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor
[patent_app_type] => utility
[patent_app_number] => 17/870926
[patent_app_country] => US
[patent_app_date] => 2022-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 10567
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870926
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/870926 | Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor | Jul 21, 2022 | Issued |
Array
(
[id] => 19228734
[patent_doc_number] => 12008372
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-11
[patent_title] => Techniques for reducing CPU privilege boundary crossings
[patent_app_type] => utility
[patent_app_number] => 17/870651
[patent_app_country] => US
[patent_app_date] => 2022-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3881
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870651
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/870651 | Techniques for reducing CPU privilege boundary crossings | Jul 20, 2022 | Issued |
Array
(
[id] => 20304021
[patent_doc_number] => 12450009
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => System and method for predication handling
[patent_app_type] => utility
[patent_app_number] => 17/867134
[patent_app_country] => US
[patent_app_date] => 2022-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867134
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/867134 | System and method for predication handling | Jul 17, 2022 | Issued |
Array
(
[id] => 18255251
[patent_doc_number] => 20230082290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => APPARATUSES, METHODS, AND SYSTEMS TO PRECISELY MONITOR MEMORY STORE ACCESSES
[patent_app_type] => utility
[patent_app_number] => 17/862708
[patent_app_country] => US
[patent_app_date] => 2022-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19863
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862708
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/862708 | APPARATUSES, METHODS, AND SYSTEMS TO PRECISELY MONITOR MEMORY STORE ACCESSES | Jul 11, 2022 | Abandoned |
Array
(
[id] => 18897281
[patent_doc_number] => 20240012766
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-11
[patent_title] => MANAGING PERIPHERAL DEVICE CONNECTIVITY BASED ON CONTEXT
[patent_app_type] => utility
[patent_app_number] => 17/811389
[patent_app_country] => US
[patent_app_date] => 2022-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6574
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17811389
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/811389 | Managing peripheral device connectivity based on context | Jul 7, 2022 | Issued |
Array
(
[id] => 19811358
[patent_doc_number] => 12242752
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Performance indicator on a data storage device
[patent_app_type] => utility
[patent_app_number] => 17/853589
[patent_app_country] => US
[patent_app_date] => 2022-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 14908
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 259
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853589
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/853589 | Performance indicator on a data storage device | Jun 28, 2022 | Issued |
Array
(
[id] => 17948544
[patent_doc_number] => 20220335563
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => GRAPHICS PROCESSING UNIT WITH NETWORK INTERFACES
[patent_app_type] => utility
[patent_app_number] => 17/853793
[patent_app_country] => US
[patent_app_date] => 2022-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12671
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853793
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/853793 | Graphics processing unit with network interfaces | Jun 28, 2022 | Issued |
Array
(
[id] => 18772900
[patent_doc_number] => 20230367726
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => Processing I/O Commands using Block Size Aware Polling
[patent_app_type] => utility
[patent_app_number] => 17/851357
[patent_app_country] => US
[patent_app_date] => 2022-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6049
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851357
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/851357 | Processing I/O commands using block size aware polling | Jun 27, 2022 | Issued |
Array
(
[id] => 19911856
[patent_doc_number] => 12288067
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-29
[patent_title] => Prediction of number of iterations of a fetching process
[patent_app_type] => utility
[patent_app_number] => 17/847378
[patent_app_country] => US
[patent_app_date] => 2022-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 22750
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17847378
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/847378 | Prediction of number of iterations of a fetching process | Jun 22, 2022 | Issued |
Array
(
[id] => 18832603
[patent_doc_number] => 20230401130
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-14
[patent_title] => FPGA BASED PLATFORM FOR POST-SILICON VALIDATION OF CHIPLETS
[patent_app_type] => utility
[patent_app_number] => 17/840211
[patent_app_country] => US
[patent_app_date] => 2022-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 32859
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840211
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/840211 | FPGA BASED PLATFORM FOR POST-SILICON VALIDATION OF CHIPLETS | Jun 13, 2022 | Pending |
Array
(
[id] => 17915618
[patent_doc_number] => 20220318014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => METHOD AND APPARATUS FOR DATA-READY MEMORY OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 17/839071
[patent_app_country] => US
[patent_app_date] => 2022-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19921
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839071
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/839071 | Method and apparatus for data-ready memory operations | Jun 12, 2022 | Issued |
Array
(
[id] => 20610124
[patent_doc_number] => 12585726
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-24
[patent_title] => Application programming interface to accelerate matrix operations
[patent_app_type] => utility
[patent_app_number] => 17/834427
[patent_app_country] => US
[patent_app_date] => 2022-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 44
[patent_no_of_words] => 45217
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834427
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/834427 | Application programming interface to accelerate matrix operations | Jun 6, 2022 | Issued |
Array
(
[id] => 17884809
[patent_doc_number] => 20220300286
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR ZEROING A MATRIX
[patent_app_type] => utility
[patent_app_number] => 17/833643
[patent_app_country] => US
[patent_app_date] => 2022-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18255
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833643
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/833643 | SYSTEMS, METHODS, AND APPARATUSES FOR ZEROING A MATRIX | Jun 5, 2022 | Abandoned |
Array
(
[id] => 18787932
[patent_doc_number] => 20230376314
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => Out-Of-Order Input / Output Write
[patent_app_type] => utility
[patent_app_number] => 17/748066
[patent_app_country] => US
[patent_app_date] => 2022-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3460
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748066
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/748066 | Out-of-order input / output write | May 18, 2022 | Issued |