Search

Thomas P. Burke

Examiner (ID: 6200, Phone: (571)270-5407 , Office: P/3741 )

Most Active Art Unit
3741
Art Unit(s)
3741
Total Applications
436
Issued Applications
152
Pending Applications
82
Abandoned Applications
217

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14692821 [patent_doc_number] => 20190245526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => LEVEL SHIFT CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/118570 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16118570 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/118570
LEVEL SHIFT CIRCUIT Aug 30, 2018 Abandoned
Array ( [id] => 15489485 [patent_doc_number] => 10560111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Nested cascaded mixed-radix digital delta-sigma modulator [patent_app_type] => utility [patent_app_number] => 16/117361 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117361 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117361
Nested cascaded mixed-radix digital delta-sigma modulator Aug 29, 2018 Issued
Array ( [id] => 15016507 [patent_doc_number] => 10454422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Differential mixer and method [patent_app_type] => utility [patent_app_number] => 16/116745 [patent_app_country] => US [patent_app_date] => 2018-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 8033 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/116745
Differential mixer and method Aug 28, 2018 Issued
Array ( [id] => 17166821 [patent_doc_number] => 11152935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => System and method to deliver reset via power line [patent_app_type] => utility [patent_app_number] => 16/115022 [patent_app_country] => US [patent_app_date] => 2018-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4229 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16115022 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/115022
System and method to deliver reset via power line Aug 27, 2018 Issued
Array ( [id] => 14860477 [patent_doc_number] => 10418982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Folded divider architecture [patent_app_type] => utility [patent_app_number] => 16/113235 [patent_app_country] => US [patent_app_date] => 2018-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5178 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16113235 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/113235
Folded divider architecture Aug 26, 2018 Issued
Array ( [id] => 14770381 [patent_doc_number] => 10396600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Power transmitter, resonance-type contactless power supply and control method therefor [patent_app_type] => utility [patent_app_number] => 16/103065 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6065 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103065 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103065
Power transmitter, resonance-type contactless power supply and control method therefor Aug 13, 2018 Issued
Array ( [id] => 15001257 [patent_doc_number] => 20190319586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => CHARGE PUMP FOR SCALING THE HIGHEST OF MULTIPLE VOLTAGES WHEN AT LEAST ONE OF THE MULTIPLE VOLTAGES VARIES [patent_app_type] => utility [patent_app_number] => 16/102741 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102741 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/102741
Charge pump for scaling the highest of multiple voltages when at least one of the multiple voltages varies Aug 13, 2018 Issued
Array ( [id] => 14604973 [patent_doc_number] => 10355686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Method and system for reliable bootstrapping switches [patent_app_type] => utility [patent_app_number] => 16/057499 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057499 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057499
Method and system for reliable bootstrapping switches Aug 6, 2018 Issued
Array ( [id] => 16200327 [patent_doc_number] => 10725486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Reference voltage generator [patent_app_type] => utility [patent_app_number] => 16/052654 [patent_app_country] => US [patent_app_date] => 2018-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 10454 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16052654 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/052654
Reference voltage generator Aug 1, 2018 Issued
Array ( [id] => 16069007 [patent_doc_number] => 10693471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Digital phase locked loop for low jitter applications [patent_app_type] => utility [patent_app_number] => 16/030970 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9212 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030970 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030970
Digital phase locked loop for low jitter applications Jul 9, 2018 Issued
Array ( [id] => 13544447 [patent_doc_number] => 20180323770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => VARIABLE FILTER [patent_app_type] => utility [patent_app_number] => 16/031911 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16031911 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/031911
Variable filter Jul 9, 2018 Issued
Array ( [id] => 16049123 [patent_doc_number] => 10686452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Digital phase locked loop for low jitter applications [patent_app_type] => utility [patent_app_number] => 16/013236 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9213 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 404 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013236 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/013236
Digital phase locked loop for low jitter applications Jun 19, 2018 Issued
Array ( [id] => 14126757 [patent_doc_number] => 10250253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Method and apparatus for a brown out detector [patent_app_type] => utility [patent_app_number] => 15/996994 [patent_app_country] => US [patent_app_date] => 2018-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15996994 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/996994
Method and apparatus for a brown out detector Jun 3, 2018 Issued
Array ( [id] => 15734729 [patent_doc_number] => 10615806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Digital phase locked loop for low jitter applications [patent_app_type] => utility [patent_app_number] => 15/994107 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9212 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994107 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/994107
Digital phase locked loop for low jitter applications May 30, 2018 Issued
Array ( [id] => 16553729 [patent_doc_number] => 10886906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-05 [patent_title] => Duty-cycle correction using balanced clocks [patent_app_type] => utility [patent_app_number] => 15/989623 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9515 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989623 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989623
Duty-cycle correction using balanced clocks May 24, 2018 Issued
Array ( [id] => 16049119 [patent_doc_number] => 10686450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Test and characterization of an embedded PLL in an SOC during startup [patent_app_type] => utility [patent_app_number] => 15/987257 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987257 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987257
Test and characterization of an embedded PLL in an SOC during startup May 22, 2018 Issued
Array ( [id] => 16433580 [patent_doc_number] => 10833683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Clock generator [patent_app_type] => utility [patent_app_number] => 15/984387 [patent_app_country] => US [patent_app_date] => 2018-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4526 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15984387 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/984387
Clock generator May 19, 2018 Issued
Array ( [id] => 15986155 [patent_doc_number] => 10673420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Electronic circuit including flip-flop using common clock [patent_app_type] => utility [patent_app_number] => 15/981415 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13309 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981415 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981415
Electronic circuit including flip-flop using common clock May 15, 2018 Issued
Array ( [id] => 15986151 [patent_doc_number] => 10673418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Level shifter circuit [patent_app_type] => utility [patent_app_number] => 15/980236 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4511 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980236 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/980236
Level shifter circuit May 14, 2018 Issued
Array ( [id] => 16418502 [patent_doc_number] => 10826412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Method for controlling power semiconductors in an inverter [patent_app_type] => utility [patent_app_number] => 15/975218 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3475 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975218 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/975218
Method for controlling power semiconductors in an inverter May 8, 2018 Issued
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