
Thomas Robbins
Examiner (ID: 16723)
| Most Active Art Unit | 2516 |
| Art Unit(s) | 2873, 2752, 2507, 2516, 2899 |
| Total Applications | 269 |
| Issued Applications | 233 |
| Pending Applications | 18 |
| Abandoned Applications | 18 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3955725
[patent_doc_number] => 05930523
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Microcomputer having multiple bus structure coupling CPU to other processing elements'
[patent_app_type] => 1
[patent_app_number] => 9/055099
[patent_app_country] => US
[patent_app_date] => 1998-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 44
[patent_no_of_words] => 32006
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/930/05930523.pdf
[firstpage_image] =>[orig_patent_app_number] => 055099
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/055099 | Microcomputer having multiple bus structure coupling CPU to other processing elements | Apr 2, 1998 | Issued |
Array
(
[id] => 4057997
[patent_doc_number] => 05913069
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Interleaving memory in distributed vector architecture multiprocessor system'
[patent_app_type] => 1
[patent_app_number] => 8/987948
[patent_app_country] => US
[patent_app_date] => 1997-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6844
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/913/05913069.pdf
[firstpage_image] =>[orig_patent_app_number] => 987948
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/987948 | Interleaving memory in distributed vector architecture multiprocessor system | Dec 9, 1997 | Issued |
Array
(
[id] => 3941053
[patent_doc_number] => 05946496
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Distributed vector architecture'
[patent_app_type] => 1
[patent_app_number] => 8/988524
[patent_app_country] => US
[patent_app_date] => 1997-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6823
[patent_no_of_claims] => 17
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[patent_words_short_claim] => 107
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[pdf_file] => patents/05/946/05946496.pdf
[firstpage_image] =>[orig_patent_app_number] => 988524
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/988524 | Distributed vector architecture | Dec 9, 1997 | Issued |
Array
(
[id] => 3952516
[patent_doc_number] => 05872993
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Communications system with multiple, simultaneous accesses to a memory'
[patent_app_type] => 1
[patent_app_number] => 8/980579
[patent_app_country] => US
[patent_app_date] => 1997-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 25
[patent_no_of_words] => 24273
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/872/05872993.pdf
[firstpage_image] =>[orig_patent_app_number] => 980579
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/980579 | Communications system with multiple, simultaneous accesses to a memory | Nov 30, 1997 | Issued |
Array
(
[id] => 4017992
[patent_doc_number] => 05859994
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Apparatus and method for modifying instruction length decoding in a computer processor'
[patent_app_type] => 1
[patent_app_number] => 8/970597
[patent_app_country] => US
[patent_app_date] => 1997-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4545
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[pdf_file] => patents/05/859/05859994.pdf
[firstpage_image] =>[orig_patent_app_number] => 970597
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/970597 | Apparatus and method for modifying instruction length decoding in a computer processor | Nov 13, 1997 | Issued |
Array
(
[id] => 3842407
[patent_doc_number] => 05784634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Pipelined CPU with instruction fetch, execution and write back stages'
[patent_app_type] => 1
[patent_app_number] => 8/967267
[patent_app_country] => US
[patent_app_date] => 1997-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/784/05784634.pdf
[firstpage_image] =>[orig_patent_app_number] => 967267
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/967267 | Pipelined CPU with instruction fetch, execution and write back stages | Nov 6, 1997 | Issued |
Array
(
[id] => 4015100
[patent_doc_number] => 05923894
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Adaptable input/output pin control'
[patent_app_type] => 1
[patent_app_number] => 8/963346
[patent_app_country] => US
[patent_app_date] => 1997-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4043
[patent_no_of_claims] => 38
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/923/05923894.pdf
[firstpage_image] =>[orig_patent_app_number] => 963346
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/963346 | Adaptable input/output pin control | Nov 2, 1997 | Issued |
| 08/957059 | EFFICIENT FLOW CONTROL MECHANISM FOR USE IN SWITCH BASED MULTIPROCESSOR SYSTEM EMPLOYING VIRTUAL CHANNELS | Oct 23, 1997 | Abandoned |
Array
(
[id] => 3772944
[patent_doc_number] => 05852740
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-22
[patent_title] => 'Polymorphic network methods and apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/951057
[patent_app_country] => US
[patent_app_date] => 1997-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 64
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[patent_no_of_words] => 22254
[patent_no_of_claims] => 2
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[pdf_file] => patents/05/852/05852740.pdf
[firstpage_image] =>[orig_patent_app_number] => 951057
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/951057 | Polymorphic network methods and apparatus | Oct 14, 1997 | Issued |
Array
(
[id] => 4081017
[patent_doc_number] => 05867652
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'Method and apparatus for supporting multiple outstanding network requests on a single connection'
[patent_app_type] => 1
[patent_app_number] => 8/953837
[patent_app_country] => US
[patent_app_date] => 1997-10-14
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[pdf_file] => patents/05/867/05867652.pdf
[firstpage_image] =>[orig_patent_app_number] => 953837
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/953837 | Method and apparatus for supporting multiple outstanding network requests on a single connection | Oct 13, 1997 | Issued |
Array
(
[id] => 4070390
[patent_doc_number] => 05864703
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-26
[patent_title] => 'Method for providing extended precision in SIMD vector arithmetic operations'
[patent_app_type] => 1
[patent_app_number] => 8/947648
[patent_app_country] => US
[patent_app_date] => 1997-10-09
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/864/05864703.pdf
[firstpage_image] =>[orig_patent_app_number] => 947648
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/947648 | Method for providing extended precision in SIMD vector arithmetic operations | Oct 8, 1997 | Issued |
Array
(
[id] => 3772930
[patent_doc_number] => 05852739
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-22
[patent_title] => 'Low profile plate interlock mechanism for a computer chassis'
[patent_app_type] => 1
[patent_app_number] => 8/947139
[patent_app_country] => US
[patent_app_date] => 1997-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/852/05852739.pdf
[firstpage_image] =>[orig_patent_app_number] => 947139
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/947139 | Low profile plate interlock mechanism for a computer chassis | Oct 7, 1997 | Issued |
Array
(
[id] => 3879008
[patent_doc_number] => 05794034
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Ordered and reliable maintenance of inter-process relationships in a distributed multiprocessor'
[patent_app_type] => 1
[patent_app_number] => 8/935617
[patent_app_country] => US
[patent_app_date] => 1997-09-23
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[pdf_file] => patents/05/794/05794034.pdf
[firstpage_image] =>[orig_patent_app_number] => 935617
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/935617 | Ordered and reliable maintenance of inter-process relationships in a distributed multiprocessor | Sep 22, 1997 | Issued |
Array
(
[id] => 3952444
[patent_doc_number] => 05872989
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[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Processor having a register configuration suited for parallel execution control of loop processing'
[patent_app_type] => 1
[patent_app_number] => 8/934061
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[firstpage_image] =>[orig_patent_app_number] => 934061
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/934061 | Processor having a register configuration suited for parallel execution control of loop processing | Sep 18, 1997 | Issued |
Array
(
[id] => 3909630
[patent_doc_number] => 05835710
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[patent_title] => 'Network interconnection apparatus, network node apparatus, and packet transfer method for high speed, large capacity inter-network communication'
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[patent_app_number] => 8/924825
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[pdf_file] => patents/05/835/05835710.pdf
[firstpage_image] =>[orig_patent_app_number] => 924825
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/924825 | Network interconnection apparatus, network node apparatus, and packet transfer method for high speed, large capacity inter-network communication | Sep 4, 1997 | Issued |
Array
(
[id] => 4015088
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[patent_title] => 'Method and apparatus for interfacing a processor to a coprocessor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/924137 | Method and apparatus for interfacing a processor to a coprocessor | Sep 4, 1997 | Issued |
Array
(
[id] => 3878670
[patent_doc_number] => 05797026
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[patent_issue_date] => 1998-08-18
[patent_title] => 'Method and apparatus for self-snooping a bus during a boundary transaction'
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[pdf_file] => patents/05/797/05797026.pdf
[firstpage_image] =>[orig_patent_app_number] => 921845
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/921845 | Method and apparatus for self-snooping a bus during a boundary transaction | Sep 1, 1997 | Issued |
Array
(
[id] => 3788834
[patent_doc_number] => 05774738
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[patent_issue_date] => 1998-06-30
[patent_title] => 'State machines'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/912498 | State machines | Aug 17, 1997 | Issued |
Array
(
[id] => 3850215
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[patent_title] => 'Method and apparatus for on the fly descriptor validation'
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[firstpage_image] =>[orig_patent_app_number] => 912264
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/912264 | Method and apparatus for on the fly descriptor validation | Aug 17, 1997 | Issued |
Array
(
[id] => 3801229
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[patent_issue_date] => 1998-11-24
[patent_title] => 'Miniature circuit card with retractable cord assembly'
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[firstpage_image] =>[orig_patent_app_number] => 903129
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/903129 | Miniature circuit card with retractable cord assembly | Jul 29, 1997 | Issued |