
Thomas S. Giampaolo Ii
Examiner (ID: 671, Phone: (303)297-4235 , Office: P/2852 )
| Most Active Art Unit | 2852 |
| Art Unit(s) | 2852 |
| Total Applications | 695 |
| Issued Applications | 583 |
| Pending Applications | 40 |
| Abandoned Applications | 95 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19452651
[patent_doc_number] => 20240312781
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => METHOD FOR MAKING A RADIO FREQUENCY SILICON-ON-INSULATOR (RFSOI) WAFER INCLUDING A SUPERLATTICE
[patent_app_type] => utility
[patent_app_number] => 18/604620
[patent_app_country] => US
[patent_app_date] => 2024-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4464
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604620
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/604620 | Method for making a radio frequency silicon-on-insulator (RFSOI) wafer including a superlattice | Mar 13, 2024 | Issued |
Array
(
[id] => 19286010
[patent_doc_number] => 20240222488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR WITH DOPED SEMICONDUCTOR REGION IN GATE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/443357
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8948
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443357
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/443357 | High electron mobility transistor with doped semiconductor region in gate structure | Feb 15, 2024 | Issued |
Array
(
[id] => 19286010
[patent_doc_number] => 20240222488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR WITH DOPED SEMICONDUCTOR REGION IN GATE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/443357
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8948
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443357
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/443357 | High electron mobility transistor with doped semiconductor region in gate structure | Feb 15, 2024 | Issued |
Array
(
[id] => 19191699
[patent_doc_number] => 20240170612
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => EPITAXIAL OXIDE TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 18/423986
[patent_app_country] => US
[patent_app_date] => 2024-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 80780
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423986
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/423986 | Epitaxial oxide transistor | Jan 25, 2024 | Issued |
Array
(
[id] => 19176167
[patent_doc_number] => 20240162141
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/419015
[patent_app_country] => US
[patent_app_date] => 2024-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10714
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419015
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/419015 | Sideways vias in isolation areas to contact interior layers in stacked devices | Jan 21, 2024 | Issued |
Array
(
[id] => 20434989
[patent_doc_number] => 12506018
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-23
[patent_title] => Apparatus and method for treating substrate
[patent_app_type] => utility
[patent_app_number] => 18/407848
[patent_app_country] => US
[patent_app_date] => 2024-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1143
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407848
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/407848 | Apparatus and method for treating substrate | Jan 8, 2024 | Issued |
Array
(
[id] => 20434989
[patent_doc_number] => 12506018
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-23
[patent_title] => Apparatus and method for treating substrate
[patent_app_type] => utility
[patent_app_number] => 18/407848
[patent_app_country] => US
[patent_app_date] => 2024-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1143
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407848
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/407848 | Apparatus and method for treating substrate | Jan 8, 2024 | Issued |
Array
(
[id] => 19873759
[patent_doc_number] => 12266630
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-01
[patent_title] => Bond pad connection layout
[patent_app_type] => utility
[patent_app_number] => 18/405875
[patent_app_country] => US
[patent_app_date] => 2024-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 3937
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18405875
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/405875 | Bond pad connection layout | Jan 4, 2024 | Issued |
Array
(
[id] => 19951584
[patent_doc_number] => 12322958
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-03
[patent_title] => Electrostatic discharge (ESD) protection circuit with disable feature based on hot-plug condition detection
[patent_app_type] => utility
[patent_app_number] => 18/396987
[patent_app_country] => US
[patent_app_date] => 2023-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 2232
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18396987
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/396987 | Electrostatic discharge (ESD) protection circuit with disable feature based on hot-plug condition detection | Dec 26, 2023 | Issued |
Array
(
[id] => 19951584
[patent_doc_number] => 12322958
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-03
[patent_title] => Electrostatic discharge (ESD) protection circuit with disable feature based on hot-plug condition detection
[patent_app_type] => utility
[patent_app_number] => 18/396987
[patent_app_country] => US
[patent_app_date] => 2023-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 2232
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18396987
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/396987 | Electrostatic discharge (ESD) protection circuit with disable feature based on hot-plug condition detection | Dec 26, 2023 | Issued |
Array
(
[id] => 19781663
[patent_doc_number] => 12230702
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Self-passivated nitrogen-polar III-nitride transistor
[patent_app_type] => utility
[patent_app_number] => 18/395249
[patent_app_country] => US
[patent_app_date] => 2023-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 82
[patent_no_of_words] => 12838
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395249
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/395249 | Self-passivated nitrogen-polar III-nitride transistor | Dec 21, 2023 | Issued |
Array
(
[id] => 19627285
[patent_doc_number] => 12166136
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-10
[patent_title] => Semiconductor device and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 18/541441
[patent_app_country] => US
[patent_app_date] => 2023-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 23
[patent_no_of_words] => 8664
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 401
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18541441
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/541441 | Semiconductor device and method of manufacturing the same | Dec 14, 2023 | Issued |
Array
(
[id] => 19086406
[patent_doc_number] => 20240113207
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-04
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/539700
[patent_app_country] => US
[patent_app_date] => 2023-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 39260
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539700
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/539700 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE | Dec 13, 2023 | Pending |
Array
(
[id] => 19086406
[patent_doc_number] => 20240113207
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-04
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/539700
[patent_app_country] => US
[patent_app_date] => 2023-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 39260
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539700
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/539700 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE | Dec 13, 2023 | Pending |
Array
(
[id] => 19038238
[patent_doc_number] => 20240088053
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/518471
[patent_app_country] => US
[patent_app_date] => 2023-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7326
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518471
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/518471 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | Nov 22, 2023 | Pending |
Array
(
[id] => 20216227
[patent_doc_number] => 12412882
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-09
[patent_title] => Buffer design for package integration
[patent_app_type] => utility
[patent_app_number] => 18/517330
[patent_app_country] => US
[patent_app_date] => 2023-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 3351
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18517330
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/517330 | Buffer design for package integration | Nov 21, 2023 | Issued |
Array
(
[id] => 19038137
[patent_doc_number] => 20240087952
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => SEMICONDUCTOR STRUCTURE WITH MATERIAL MODIFICATION AND LOW RESISTANCE PLUG
[patent_app_type] => utility
[patent_app_number] => 18/514164
[patent_app_country] => US
[patent_app_date] => 2023-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8598
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514164
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/514164 | Semiconductor structure with material modification and low resistance plug | Nov 19, 2023 | Issued |
Array
(
[id] => 19036140
[patent_doc_number] => 20240085955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => DEVICE ARRAY SUBSTRATE AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/513618
[patent_app_country] => US
[patent_app_date] => 2023-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4993
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513618
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/513618 | Device array substrate and display device | Nov 18, 2023 | Issued |
Array
(
[id] => 19036140
[patent_doc_number] => 20240085955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => DEVICE ARRAY SUBSTRATE AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/513618
[patent_app_country] => US
[patent_app_date] => 2023-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4993
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513618
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/513618 | Device array substrate and display device | Nov 18, 2023 | Issued |
Array
(
[id] => 19038181
[patent_doc_number] => 20240087996
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/510204
[patent_app_country] => US
[patent_app_date] => 2023-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 38867
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510204
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/510204 | Semiconductor device | Nov 14, 2023 | Issued |