Search

Thong Quoc Le

Examiner (ID: 5747, Phone: (571)272-1783 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827
Total Applications
2912
Issued Applications
2782
Pending Applications
79
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14175563 [patent_doc_number] => 10261796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Processor and method for executing in-memory copy instructions indicating on-chip or off-chip memory [patent_app_type] => utility [patent_app_number] => 15/360245 [patent_app_country] => US [patent_app_date] => 2016-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 8219 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15360245 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/360245
Processor and method for executing in-memory copy instructions indicating on-chip or off-chip memory Nov 22, 2016 Issued
Array ( [id] => 12757297 [patent_doc_number] => 20180144267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => METHODS, SYSTEMS AND APPARATUS TO IMPROVE MULTI-DEMOGRAPHIC MODELING EFFICIENCY [patent_app_type] => utility [patent_app_number] => 15/359971 [patent_app_country] => US [patent_app_date] => 2016-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359971 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359971
Methods, systems and apparatus to improve multi-demographic modeling efficiency Nov 22, 2016 Issued
Array ( [id] => 12755986 [patent_doc_number] => 20180143829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => BUFFERLESS COMMUNICATION FOR REDUNDANT MULTITHREADING USING REGISTER PERMUTATION [patent_app_type] => utility [patent_app_number] => 15/359236 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359236 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359236
Bufferless communication for redundant multithreading using register permutation Nov 21, 2016 Issued
Array ( [id] => 13484427 [patent_doc_number] => 20180293756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => ENHANCED LOCALIZATION METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 15/567596 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15567596 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/567596
ENHANCED LOCALIZATION METHOD AND APPARATUS Nov 17, 2016 Abandoned
Array ( [id] => 12688660 [patent_doc_number] => 20180121386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => SUPER SINGLE INSTRUCTION MULTIPLE DATA (SUPER-SIMD) FOR GRAPHICS PROCESSING UNIT (GPU) COMPUTING [patent_app_type] => utility [patent_app_number] => 15/354560 [patent_app_country] => US [patent_app_date] => 2016-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15354560 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/354560
SUPER SINGLE INSTRUCTION MULTIPLE DATA (SUPER-SIMD) FOR GRAPHICS PROCESSING UNIT (GPU) COMPUTING Nov 16, 2016 Abandoned
Array ( [id] => 13948433 [patent_doc_number] => 10209991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Instruction set and micro-architecture supporting asynchronous memory access [patent_app_type] => utility [patent_app_number] => 15/353161 [patent_app_country] => US [patent_app_date] => 2016-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7725 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15353161 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/353161
Instruction set and micro-architecture supporting asynchronous memory access Nov 15, 2016 Issued
Array ( [id] => 13752187 [patent_doc_number] => 10169040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => System and method for sample rate conversion [patent_app_type] => utility [patent_app_number] => 15/352598 [patent_app_country] => US [patent_app_date] => 2016-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7511 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15352598 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/352598
System and method for sample rate conversion Nov 15, 2016 Issued
Array ( [id] => 12735301 [patent_doc_number] => 20180136934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => Data Processing System and Method for Controlling an Execution Flow [patent_app_type] => utility [patent_app_number] => 15/352517 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15352517 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/352517
Data processing system and method for executing block call and block return instructions Nov 14, 2016 Issued
Array ( [id] => 16248180 [patent_doc_number] => 10747539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-18 [patent_title] => Scan-on-fill next fetch target prediction [patent_app_type] => utility [patent_app_number] => 15/350486 [patent_app_country] => US [patent_app_date] => 2016-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15350486 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/350486
Scan-on-fill next fetch target prediction Nov 13, 2016 Issued
Array ( [id] => 13664949 [patent_doc_number] => 10162636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Control apparatus, integrated circuit and management method for stack [patent_app_type] => utility [patent_app_number] => 15/345520 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7496 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345520 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345520
Control apparatus, integrated circuit and management method for stack Nov 7, 2016 Issued
Array ( [id] => 13029177 [patent_doc_number] => 10037208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Multi-element instruction with different read and write masks [patent_app_type] => utility [patent_app_number] => 15/346531 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 15179 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15346531 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/346531
Multi-element instruction with different read and write masks Nov 7, 2016 Issued
Array ( [id] => 16446942 [patent_doc_number] => 10838871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Hardware processor architecture having a hint cache [patent_app_type] => utility [patent_app_number] => 15/344624 [patent_app_country] => US [patent_app_date] => 2016-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15344624 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/344624
Hardware processor architecture having a hint cache Nov 6, 2016 Issued
Array ( [id] => 17288560 [patent_doc_number] => 11205110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Device/server deployment of neural network data entry system [patent_app_type] => utility [patent_app_number] => 15/332907 [patent_app_country] => US [patent_app_date] => 2016-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15332907 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/332907
Device/server deployment of neural network data entry system Oct 23, 2016 Issued
Array ( [id] => 13281477 [patent_doc_number] => 10152323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Method and apparatus for shuffling data [patent_app_type] => utility [patent_app_number] => 15/299914 [patent_app_country] => US [patent_app_date] => 2016-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 43 [patent_no_of_words] => 19923 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15299914 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/299914
Method and apparatus for shuffling data Oct 20, 2016 Issued
Array ( [id] => 11438052 [patent_doc_number] => 20170039073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'PROCESSING BYPASS DIRECTORY TRACKING SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/297045 [patent_app_country] => US [patent_app_date] => 2016-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297045 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/297045
PROCESSING BYPASS DIRECTORY TRACKING SYSTEM AND METHOD Oct 17, 2016 Abandoned
Array ( [id] => 11396957 [patent_doc_number] => 20170017493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'VARIABLE UPDATES OF BRANCH PREDICTION STATES' [patent_app_type] => utility [patent_app_number] => 15/286752 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6014 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15286752 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/286752
Variable updates of branch prediction states Oct 5, 2016 Issued
Array ( [id] => 11385246 [patent_doc_number] => 20170011300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'DEVICE MANAGEMENT METHOD AND DEVICE MANAGEMENT APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/267853 [patent_app_country] => US [patent_app_date] => 2016-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 22865 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267853 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/267853
Device management method and device management apparatus Sep 15, 2016 Issued
Array ( [id] => 11731943 [patent_doc_number] => 20170193386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'WEBSITE ADDRESS IDENTIFICATION METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/246261 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6842 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15246261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/246261
Website address identification method and apparatus Aug 23, 2016 Issued
Array ( [id] => 11430899 [patent_doc_number] => 09569215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-14 [patent_title] => 'Method of synchronizing independent functional unit' [patent_app_type] => utility [patent_app_number] => 15/237026 [patent_app_country] => US [patent_app_date] => 2016-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3397 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15237026 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/237026
Method of synchronizing independent functional unit Aug 14, 2016 Issued
Array ( [id] => 11889817 [patent_doc_number] => 09760378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Methods and computer systems of software level superscalar out-of-order processing' [patent_app_type] => utility [patent_app_number] => 15/228082 [patent_app_country] => US [patent_app_date] => 2016-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15228082 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/228082
Methods and computer systems of software level superscalar out-of-order processing Aug 3, 2016 Issued
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