Search

Thong Quoc Le

Examiner (ID: 7338, Phone: (571)272-1783 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827
Total Applications
2911
Issued Applications
2782
Pending Applications
78
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15108341 [patent_doc_number] => 10475500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Memory cell imprint avoidance [patent_app_type] => utility [patent_app_number] => 16/111021 [patent_app_country] => US [patent_app_date] => 2018-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 18028 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111021 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/111021
Memory cell imprint avoidance Aug 22, 2018 Issued
Array ( [id] => 15167635 [patent_doc_number] => 10489312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Stack access control for memory device [patent_app_type] => utility [patent_app_number] => 16/107963 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107963 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107963
Stack access control for memory device Aug 20, 2018 Issued
Array ( [id] => 13784935 [patent_doc_number] => 20190006006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => APPARATUSES INCLUDING MEMORY CELLS AND METHODS OF OPERATION OF SAME [patent_app_type] => utility [patent_app_number] => 16/105874 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105874 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105874
Apparatuses including memory cells and methods of operation of same Aug 19, 2018 Issued
Array ( [id] => 15672441 [patent_doc_number] => 10600458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Memory device and method of operating the same for latency control [patent_app_type] => utility [patent_app_number] => 16/105368 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 10163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105368 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105368
Memory device and method of operating the same for latency control Aug 19, 2018 Issued
Array ( [id] => 14644017 [patent_doc_number] => 10366756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-30 [patent_title] => Control circuit used for ternary content-addressable memory with two logic units [patent_app_type] => utility [patent_app_number] => 16/104946 [patent_app_country] => US [patent_app_date] => 2018-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5131 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16104946 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/104946
Control circuit used for ternary content-addressable memory with two logic units Aug 18, 2018 Issued
Array ( [id] => 14706653 [patent_doc_number] => 10381084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/056835 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 35 [patent_no_of_words] => 14187 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056835 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056835
Semiconductor memory device Aug 6, 2018 Issued
Array ( [id] => 14919963 [patent_doc_number] => 10431308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-01 [patent_title] => Memory cell size reduction for scalable logic gate non-volatile memory arrays [patent_app_type] => utility [patent_app_number] => 16/055614 [patent_app_country] => US [patent_app_date] => 2018-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 5728 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16055614 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/055614
Memory cell size reduction for scalable logic gate non-volatile memory arrays Aug 5, 2018 Issued
Array ( [id] => 15474791 [patent_doc_number] => 10553278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-04 [patent_title] => Media manager cache eviction timer for reads and writes during resistivity drift [patent_app_type] => utility [patent_app_number] => 16/056354 [patent_app_country] => US [patent_app_date] => 2018-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056354 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056354
Media manager cache eviction timer for reads and writes during resistivity drift Aug 5, 2018 Issued
Array ( [id] => 15060941 [patent_doc_number] => 10460782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-29 [patent_title] => Integrated circuits having single state memory reference cells and methods for operating the same [patent_app_type] => utility [patent_app_number] => 16/055952 [patent_app_country] => US [patent_app_date] => 2018-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16055952 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/055952
Integrated circuits having single state memory reference cells and methods for operating the same Aug 5, 2018 Issued
Array ( [id] => 13570799 [patent_doc_number] => 20180336947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => TEMPERATURE GRADIENTS FOR CONTROLLING MEMRISTOR SWITCHING [patent_app_type] => utility [patent_app_number] => 16/048502 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048502 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/048502
TEMPERATURE GRADIENTS FOR CONTROLLING MEMRISTOR SWITCHING Jul 29, 2018 Abandoned
Array ( [id] => 14397331 [patent_doc_number] => 10311954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Memory cell architecture for multilevel cell programming [patent_app_type] => utility [patent_app_number] => 16/045526 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14247 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/045526
Memory cell architecture for multilevel cell programming Jul 24, 2018 Issued
Array ( [id] => 15518891 [patent_doc_number] => 10566039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 16/043474 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043474 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/043474
Memory device Jul 23, 2018 Issued
Array ( [id] => 15199895 [patent_doc_number] => 10497449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Apparatus and process for controlling sense current in a non-volatile memory [patent_app_type] => utility [patent_app_number] => 16/043218 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5474 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043218 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/043218
Apparatus and process for controlling sense current in a non-volatile memory Jul 23, 2018 Issued
Array ( [id] => 15199871 [patent_doc_number] => 10497437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-03 [patent_title] => Decoding scheme for 3D cross-point memory array [patent_app_type] => utility [patent_app_number] => 16/043692 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 11846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/043692
Decoding scheme for 3D cross-point memory array Jul 23, 2018 Issued
Array ( [id] => 15442225 [patent_doc_number] => 20200035296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => DEVICE COMPRISING POLYMORPHIC RESISTIVE CELLS [patent_app_type] => utility [patent_app_number] => 16/043254 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043254 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/043254
Device comprising polymorphic resistive cells Jul 23, 2018 Issued
Array ( [id] => 13597743 [patent_doc_number] => 20180350420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => ARRAY DATA BIT INVERSION [patent_app_type] => utility [patent_app_number] => 16/035135 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035135 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035135
Array data bit inversion Jul 12, 2018 Issued
Array ( [id] => 13527857 [patent_doc_number] => 20180315471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/030943 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030943 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030943
Semiconductor storage device Jul 9, 2018 Issued
Array ( [id] => 15214457 [patent_doc_number] => 20190369915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A SINGLE COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 16/030740 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030740
Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same Jul 8, 2018 Issued
Array ( [id] => 14800741 [patent_doc_number] => 10403379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Erased block reverification method for solid state storage device [patent_app_type] => utility [patent_app_number] => 16/029784 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5187 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029784
Erased block reverification method for solid state storage device Jul 8, 2018 Issued
Array ( [id] => 14525465 [patent_doc_number] => 10340003 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-02 [patent_title] => Input-pattern aware reference generation system and computing-in-memory system including the same [patent_app_type] => utility [patent_app_number] => 16/029350 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4973 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029350
Input-pattern aware reference generation system and computing-in-memory system including the same Jul 5, 2018 Issued
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