
Thong Quoc Le
Examiner (ID: 5725, Phone: (571)272-1783 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827 |
| Total Applications | 2906 |
| Issued Applications | 2764 |
| Pending Applications | 98 |
| Abandoned Applications | 83 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19252518
[patent_doc_number] => 20240203515
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-20
[patent_title] => ONE-TIME PROGRAMMABLE MEMORY CIRCUIT, ONE-TIME PROGRAMMABLE MEMORY AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/539622
[patent_app_country] => US
[patent_app_date] => 2023-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6702
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539622
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/539622 | ONE-TIME PROGRAMMABLE MEMORY CIRCUIT, ONE-TIME PROGRAMMABLE MEMORY AND OPERATION METHOD THEREOF | Dec 13, 2023 | Pending |
Array
(
[id] => 19118503
[patent_doc_number] => 20240130253
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => PHASE CHANGE MEMORY, ELECTRONIC DEVICE, AND PREPARATION METHOD FOR PHASE CHANGE MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/539657
[patent_app_country] => US
[patent_app_date] => 2023-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8797
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539657
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/539657 | PHASE CHANGE MEMORY, ELECTRONIC DEVICE, AND PREPARATION METHOD FOR PHASE CHANGE MEMORY | Dec 13, 2023 | Pending |
Array
(
[id] => 19069343
[patent_doc_number] => 20240103769
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => Data Writing Method and Storage Device
[patent_app_type] => utility
[patent_app_number] => 18/529831
[patent_app_country] => US
[patent_app_date] => 2023-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9472
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529831
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/529831 | Data writing method and storage device | Dec 4, 2023 | Issued |
Array
(
[id] => 19070830
[patent_doc_number] => 20240105256
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => MEMORY AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/530200
[patent_app_country] => US
[patent_app_date] => 2023-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7872
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530200
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/530200 | MEMORY AND MEMORY SYSTEM | Dec 4, 2023 | Pending |
Array
(
[id] => 19223570
[patent_doc_number] => 20240188274
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => MEMORY DEVICE HAVING TIERS OF 2-TRANSISTOR MEMORY CELLS AND CHARGE STORAGE STRUCTURE HAVING MULTIPLE PORTIONS
[patent_app_type] => utility
[patent_app_number] => 18/523069
[patent_app_country] => US
[patent_app_date] => 2023-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16330
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523069
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/523069 | Memory device having tiers of 2-transistor memory cells and charge storage structure having multiple portions | Nov 28, 2023 | Issued |
Array
(
[id] => 19221205
[patent_doc_number] => 20240185909
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => COMMAND CLOCK STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/520175
[patent_app_country] => US
[patent_app_date] => 2023-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9757
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520175
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/520175 | COMMAND CLOCK STRUCTURE | Nov 26, 2023 | Pending |
Array
(
[id] => 20345809
[patent_doc_number] => 12469544
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-11
[patent_title] => Sense amplifier circuitry and threshold voltage compensation
[patent_app_type] => utility
[patent_app_number] => 18/506202
[patent_app_country] => US
[patent_app_date] => 2023-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18506202
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/506202 | Sense amplifier circuitry and threshold voltage compensation | Nov 9, 2023 | Issued |
Array
(
[id] => 19175864
[patent_doc_number] => 20240161838
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => MEDIA MANAGEMENT SCANNING WITH UNIFIED CRITERIA TO ALLEVIATE FAST AND LATENT READ DISTURB
[patent_app_type] => utility
[patent_app_number] => 18/505855
[patent_app_country] => US
[patent_app_date] => 2023-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13340
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505855
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/505855 | MEDIA MANAGEMENT SCANNING WITH UNIFIED CRITERIA TO ALLEVIATE FAST AND LATENT READ DISTURB | Nov 8, 2023 | Pending |
Array
(
[id] => 19175840
[patent_doc_number] => 20240161814
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => NON-VOLATILE MEMORY AND REFERENCE CURRENT GENERATOR THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/505143
[patent_app_country] => US
[patent_app_date] => 2023-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12527
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505143
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/505143 | Non-volatile memory and reference current generator thereof | Nov 8, 2023 | Issued |
Array
(
[id] => 20010864
[patent_doc_number] => 20250149086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-08
[patent_title] => SEMICONDUCTOR DEVICE AND PROGRAMMABLE MACRO CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/505064
[patent_app_country] => US
[patent_app_date] => 2023-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1976
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505064
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/505064 | SEMICONDUCTOR DEVICE AND PROGRAMMABLE MACRO CIRCUIT | Nov 7, 2023 | Pending |
Array
(
[id] => 19175839
[patent_doc_number] => 20240161813
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => SENSE AMPLIFIER AND NONVOLATILE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/502661
[patent_app_country] => US
[patent_app_date] => 2023-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5512
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502661
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/502661 | SENSE AMPLIFIER AND NONVOLATILE MEMORY DEVICE | Nov 5, 2023 | Pending |
Array
(
[id] => 19661780
[patent_doc_number] => 20240428845
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-26
[patent_title] => MEMORY CONTROLLER, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/499219
[patent_app_country] => US
[patent_app_date] => 2023-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7105
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499219
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/499219 | MEMORY CONTROLLER, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF | Oct 31, 2023 | Pending |
Array
(
[id] => 19100763
[patent_doc_number] => 20240119991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => Dynamic Refresh Rate Control
[patent_app_type] => utility
[patent_app_number] => 18/488656
[patent_app_country] => US
[patent_app_date] => 2023-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6825
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488656
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/488656 | Dynamic Refresh Rate Control | Oct 16, 2023 | Pending |
Array
(
[id] => 19308745
[patent_doc_number] => 20240237328
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2024-07-11
[patent_title] => MEMORY CIRCUIT, DYNAMIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/485324
[patent_app_country] => US
[patent_app_date] => 2023-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3979
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18485324
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/485324 | Memory circuit, dynamic random access memory and operation method thereof | Oct 11, 2023 | Issued |
Array
(
[id] => 19308745
[patent_doc_number] => 20240237328
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2024-07-11
[patent_title] => MEMORY CIRCUIT, DYNAMIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/485324
[patent_app_country] => US
[patent_app_date] => 2023-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3979
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18485324
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/485324 | Memory circuit, dynamic random access memory and operation method thereof | Oct 11, 2023 | Issued |
Array
(
[id] => 20080632
[patent_doc_number] => 12354707
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Word line structures for three-dimensional memory arrays
[patent_app_type] => utility
[patent_app_number] => 18/377279
[patent_app_country] => US
[patent_app_date] => 2023-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 18039
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18377279
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/377279 | Word line structures for three-dimensional memory arrays | Oct 4, 2023 | Issued |
Array
(
[id] => 19618934
[patent_doc_number] => 20240404614
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => SEMICONDUCTOR DEVICE PROVIDING A TEST MODE RELATED TO DETECTING A DEFECT IN A METAL LINE
[patent_app_type] => utility
[patent_app_number] => 18/480027
[patent_app_country] => US
[patent_app_date] => 2023-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5060
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18480027
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/480027 | Semiconductor device providing a test mode related to detecting a defect in a metal line | Oct 2, 2023 | Issued |
Array
(
[id] => 19114957
[patent_doc_number] => 20240126707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A SINGLE COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/373769
[patent_app_country] => US
[patent_app_date] => 2023-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5142
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373769
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/373769 | Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same | Sep 26, 2023 | Issued |
Array
(
[id] => 19783266
[patent_doc_number] => 12232321
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Semiconductor memory device
[patent_app_type] => utility
[patent_app_number] => 18/475335
[patent_app_country] => US
[patent_app_date] => 2023-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 9002
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475335
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/475335 | Semiconductor memory device | Sep 26, 2023 | Issued |
Array
(
[id] => 19116153
[patent_doc_number] => 20240127903
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => DYNAMIC, RANDOM-ACCESS MEMORY WITH HIDDEN MEMORY SCRUBBING
[patent_app_type] => utility
[patent_app_number] => 18/474643
[patent_app_country] => US
[patent_app_date] => 2023-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4612
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474643
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/474643 | DYNAMIC, RANDOM-ACCESS MEMORY WITH HIDDEN MEMORY SCRUBBING | Sep 25, 2023 | Pending |