Thong Quoc Le

Array ( [id] => 13754465 [patent_doc_number] => 10170184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-01 [patent_title] => Resistive memory apparatus and setting method for resistive memory cell thereof [patent_app_type] => utility [patent_app_number] => 15/729676 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4077 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15729676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13666647 [patent_doc_number] => 10163496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Static random access memory (SRAM) tracking cells and methods of forming the same [patent_app_type] => utility [patent_app_number] => 15/728345 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 12047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14011265 [patent_doc_number] => 10224107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-05 [patent_title] => Method and apparatus for dynamically determining start program voltages for a memory device [patent_app_type] => utility [patent_app_number] => 15/720984 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 17730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14768643 [patent_doc_number] => 10395722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Reading from a mode register having different read and write timing [patent_app_type] => utility [patent_app_number] => 15/721052 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 15320 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14093643 [patent_doc_number] => 10242734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-26 [patent_title] => Resuming storage die programming after power loss [patent_app_type] => utility [patent_app_number] => 15/720492 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6819 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16690328 [patent_doc_number] => 20210072806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => AUTOMATIC VENT FOR SSD COOLING ENHANCEMENT [patent_app_type] => utility [patent_app_number] => 16/642161 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16642161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13201077 [patent_doc_number] => 10115459 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-30 [patent_title] => Multiple liner interconnects for three dimensional memory devices and method of making thereof [patent_app_type] => utility [patent_app_number] => 15/720556 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 42 [patent_no_of_words] => 18222 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14135883 [patent_doc_number] => 20190102331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => MEMORY CHANNEL HAVING MORE THAN ONE DIMM PER MOTHERBOARD DIMM CONNECTOR [patent_app_type] => utility [patent_app_number] => 15/719742 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719742 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12475131 [patent_doc_number] => 09990295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Method for increasing cache size [patent_app_type] => utility [patent_app_number] => 15/715311 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 8804 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13042879 [patent_doc_number] => 10043579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Nonvolatile semiconductor memory device [patent_app_type] => utility [patent_app_number] => 15/706250 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 35 [patent_no_of_words] => 15235 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13950295 [patent_doc_number] => 10210926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-19 [patent_title] => Tracking of optimum read voltage thresholds in nand flash devices [patent_app_type] => utility [patent_app_number] => 15/705678 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 22493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13667995 [patent_doc_number] => 10164180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Variable resistance element and memory device [patent_app_type] => utility [patent_app_number] => 15/704802 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4998 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12871840 [patent_doc_number] => 20180182455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => METHOD FOR CONTROLLING RESISTIVE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/705226 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16249242 [patent_doc_number] => 10748614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Semiconductor device and programming method therefor [patent_app_type] => utility [patent_app_number] => 16/324782 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 7808 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16324782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13143367 [patent_doc_number] => 10089016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Method of operation for a nonvolatile memory system and method of operating a memory controller [patent_app_type] => utility [patent_app_number] => 15/688939 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 13064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15688939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13131627 [patent_doc_number] => 10083752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Apparatuses and methods for efficient write in a cross-point array [patent_app_type] => utility [patent_app_number] => 15/690044 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 9464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13893121 [patent_doc_number] => 10199112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-05 [patent_title] => Sense amplifier circuit for reading data in a flash memory cell [patent_app_type] => utility [patent_app_number] => 15/687092 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8105 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13158193 [patent_doc_number] => 10095823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Electronic device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/686644 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 15524 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13173551 [patent_doc_number] => 10102895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-16 [patent_title] => Back gate biasing magneto-resistive random access memory (MRAM) bit cells to reduce or avoid write operation failures caused by source degeneration [patent_app_type] => utility [patent_app_number] => 15/686424 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 12307 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13292925 [patent_doc_number] => 10157661 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-18 [patent_title] => Mitigating line-to-line capacitive coupling in a memory die [patent_app_type] => utility [patent_app_number] => 15/686996 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686996 [rel_patent_id] =>[rel_patent_doc_number] =>)