Search

Thong Quoc Le

Examiner (ID: 18725, Phone: (571)272-1783 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2818
Total Applications
2911
Issued Applications
2782
Pending Applications
78
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13708737 [patent_doc_number] => 20170365323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => MEMORY CELL IMPRINT AVOIDANCE [patent_app_type] => utility [patent_app_number] => 15/645106 [patent_app_country] => US [patent_app_date] => 2017-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15645106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/645106
Memory cell imprint avoidance Jul 9, 2017 Issued
Array ( [id] => 13042853 [patent_doc_number] => 10043566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Array data bit inversion [patent_app_type] => utility [patent_app_number] => 15/641020 [patent_app_country] => US [patent_app_date] => 2017-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 19930 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641020 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/641020
Array data bit inversion Jul 2, 2017 Issued
Array ( [id] => 12775168 [patent_doc_number] => 20180150224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => MEMORY SYSTEM AND OPERATION METHOD FOR THE SAME [patent_app_type] => utility [patent_app_number] => 15/636756 [patent_app_country] => US [patent_app_date] => 2017-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15636756 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/636756
Memory system and operation method for the same Jun 28, 2017 Issued
Array ( [id] => 13173547 [patent_doc_number] => 10102893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Systems for implementing word line pulse techniques in magnetoelectric junctions [patent_app_type] => utility [patent_app_number] => 15/636568 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9839 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15636568 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/636568
Systems for implementing word line pulse techniques in magnetoelectric junctions Jun 27, 2017 Issued
Array ( [id] => 13787009 [patent_doc_number] => 20190007043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => Circuit with Impedance Elements Connected to Sources and Drains of PMOSFET Headers [patent_app_type] => utility [patent_app_number] => 15/636428 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15636428 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/636428
Circuit with impedance elements connected to sources and drains of pMOSFET headers Jun 27, 2017 Issued
Array ( [id] => 13030375 [patent_doc_number] => 10037810 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-31 [patent_title] => Method and apparatus for coupling up a voltage-setting transistor for a control line in a programming operation [patent_app_type] => utility [patent_app_number] => 15/634006 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 32 [patent_no_of_words] => 12937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15634006 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/634006
Method and apparatus for coupling up a voltage-setting transistor for a control line in a programming operation Jun 26, 2017 Issued
Array ( [id] => 13111535 [patent_doc_number] => 10074425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Page programming sequences and assignment schemes for a memory device [patent_app_type] => utility [patent_app_number] => 15/632009 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2772 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632009 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/632009
Page programming sequences and assignment schemes for a memory device Jun 22, 2017 Issued
Array ( [id] => 11983398 [patent_doc_number] => 20170287553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/627535 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6596 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627535
Semiconductor device Jun 19, 2017 Issued
Array ( [id] => 12249923 [patent_doc_number] => 09922705 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-20 [patent_title] => 'Reducing select gate injection disturb at the beginning of an erase operation' [patent_app_type] => utility [patent_app_number] => 15/621222 [patent_app_country] => US [patent_app_date] => 2017-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 14961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15621222 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/621222
Reducing select gate injection disturb at the beginning of an erase operation Jun 12, 2017 Issued
Array ( [id] => 12263547 [patent_doc_number] => 20180082744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/620886 [patent_app_country] => US [patent_app_date] => 2017-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620886 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/620886
Semiconductor memory device Jun 12, 2017 Issued
Array ( [id] => 12122121 [patent_doc_number] => 20180005706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'Methods for Error Correction with Resistive Change Element Arrays' [patent_app_type] => utility [patent_app_number] => 15/621788 [patent_app_country] => US [patent_app_date] => 2017-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 70 [patent_no_of_words] => 46149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15621788 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/621788
Methods for error correction with resistive change element arrays Jun 12, 2017 Issued
Array ( [id] => 13708805 [patent_doc_number] => 20170365357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => MAGNETIC MEMORY DEVICE AND CONTROLLING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/620295 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620295 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/620295
Magnetic memory device and controlling method thereof Jun 11, 2017 Issued
Array ( [id] => 12822928 [patent_doc_number] => 20180166148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => CONTROL METHOD FOR MEMORY DEVICE AND MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 15/614654 [patent_app_country] => US [patent_app_date] => 2017-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15614654 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/614654
Control method for memory device and memory controller Jun 5, 2017 Issued
Array ( [id] => 14011231 [patent_doc_number] => 10224090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Directed per bank refresh command [patent_app_type] => utility [patent_app_number] => 15/611455 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 9426 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15611455 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/611455
Directed per bank refresh command May 31, 2017 Issued
Array ( [id] => 11959154 [patent_doc_number] => 20170263307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/606903 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12225 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606903 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/606903
Semiconductor storage device May 25, 2017 Issued
Array ( [id] => 13817767 [patent_doc_number] => 10185652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Stack access control for memory device [patent_app_type] => utility [patent_app_number] => 15/606956 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4610 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606956 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/606956
Stack access control for memory device May 25, 2017 Issued
Array ( [id] => 13515811 [patent_doc_number] => 20180309448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => DATA TRANSMISSION WITH POWER SUPPLY NOISE COMPENSATION [patent_app_type] => utility [patent_app_number] => 15/496848 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496848 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496848
Data transmission with power supply noise compensation Apr 24, 2017 Issued
Array ( [id] => 13098615 [patent_doc_number] => 10068650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-04 [patent_title] => Characterizing and operating a non-volatile memory device [patent_app_type] => utility [patent_app_number] => 15/484038 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15484038 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/484038
Characterizing and operating a non-volatile memory device Apr 9, 2017 Issued
Array ( [id] => 12456594 [patent_doc_number] => 09984734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Programmable integrated circuits with in-operation reconfiguration capability [patent_app_type] => utility [patent_app_number] => 15/471325 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7914 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471325 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471325
Programmable integrated circuits with in-operation reconfiguration capability Mar 27, 2017 Issued
Array ( [id] => 11731233 [patent_doc_number] => 20170192676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/462300 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9902 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462300 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/462300
Nonvolatile semiconductor memory device Mar 16, 2017 Issued
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