
Thor B. Nielsen
Examiner (ID: 7788, Phone: (571)270-3476 , Office: P/1616 )
| Most Active Art Unit | 1616 |
| Art Unit(s) | 1616 |
| Total Applications | 388 |
| Issued Applications | 208 |
| Pending Applications | 0 |
| Abandoned Applications | 182 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6209418
[patent_doc_number] => 20020072224
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-13
[patent_title] => 'Method for improving local interconnects of multi-level interconnects process'
[patent_app_type] => new
[patent_app_number] => 09/731018
[patent_app_country] => US
[patent_app_date] => 2000-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1471
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0072/20020072224.pdf
[firstpage_image] =>[orig_patent_app_number] => 09731018
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/731018 | Method for improving local interconnects of multi-level interconnects process | Dec 6, 2000 | Abandoned |
Array
(
[id] => 1514600
[patent_doc_number] => 06420281
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-07-16
[patent_title] => 'Method of forming oxidized film on SOI substrate'
[patent_app_type] => B2
[patent_app_number] => 09/729778
[patent_app_country] => US
[patent_app_date] => 2000-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 30
[patent_no_of_words] => 4570
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/420/06420281.pdf
[firstpage_image] =>[orig_patent_app_number] => 09729778
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/729778 | Method of forming oxidized film on SOI substrate | Dec 5, 2000 | Issued |
Array
(
[id] => 1450061
[patent_doc_number] => 06455414
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Method for improving the adhesion of sputtered copper films to CVD transition metal based underlayers'
[patent_app_type] => B1
[patent_app_number] => 09/723878
[patent_app_country] => US
[patent_app_date] => 2000-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6102
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/455/06455414.pdf
[firstpage_image] =>[orig_patent_app_number] => 09723878
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/723878 | Method for improving the adhesion of sputtered copper films to CVD transition metal based underlayers | Nov 27, 2000 | Issued |
Array
(
[id] => 1588644
[patent_doc_number] => 06482665
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-19
[patent_title] => 'Polarization switching surface-emitting laser and a method of manufacturing the same'
[patent_app_type] => B1
[patent_app_number] => 09/718188
[patent_app_country] => US
[patent_app_date] => 2000-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 2410
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 396
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/482/06482665.pdf
[firstpage_image] =>[orig_patent_app_number] => 09718188
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/718188 | Polarization switching surface-emitting laser and a method of manufacturing the same | Nov 20, 2000 | Issued |
Array
(
[id] => 1397270
[patent_doc_number] => 06531396
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-11
[patent_title] => 'Method of fabricating a nickel/platinum monsilicide film'
[patent_app_type] => B1
[patent_app_number] => 09/716632
[patent_app_country] => US
[patent_app_date] => 2000-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2055
[patent_no_of_claims] => 13
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/531/06531396.pdf
[firstpage_image] =>[orig_patent_app_number] => 09716632
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/716632 | Method of fabricating a nickel/platinum monsilicide film | Nov 16, 2000 | Issued |
Array
(
[id] => 7643986
[patent_doc_number] => 06429052
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Method of making high performance transistor with a reduced width gate electrode and device comprising same'
[patent_app_type] => B1
[patent_app_number] => 09/711401
[patent_app_country] => US
[patent_app_date] => 2000-11-13
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/429/06429052.pdf
[firstpage_image] =>[orig_patent_app_number] => 09711401
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/711401 | Method of making high performance transistor with a reduced width gate electrode and device comprising same | Nov 12, 2000 | Issued |
Array
(
[id] => 1228174
[patent_doc_number] => 06696317
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-24
[patent_title] => 'Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin'
[patent_app_type] => B1
[patent_app_number] => 09/704521
[patent_app_country] => US
[patent_app_date] => 2000-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 96
[patent_no_of_words] => 7484
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/696/06696317.pdf
[firstpage_image] =>[orig_patent_app_number] => 09704521
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/704521 | Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin | Nov 2, 2000 | Issued |
Array
(
[id] => 1534512
[patent_doc_number] => 06489195
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Method for fabricating DRAM cell using a protection layer'
[patent_app_type] => B1
[patent_app_number] => 09/702795
[patent_app_country] => US
[patent_app_date] => 2000-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 6478
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/489/06489195.pdf
[firstpage_image] =>[orig_patent_app_number] => 09702795
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/702795 | Method for fabricating DRAM cell using a protection layer | Oct 31, 2000 | Issued |
Array
(
[id] => 1414881
[patent_doc_number] => 06521537
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'Modification to fill layers for inlaying semiconductor patterns'
[patent_app_type] => B1
[patent_app_number] => 09/703210
[patent_app_country] => US
[patent_app_date] => 2000-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2918
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[pdf_file] => patents/06/521/06521537.pdf
[firstpage_image] =>[orig_patent_app_number] => 09703210
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/703210 | Modification to fill layers for inlaying semiconductor patterns | Oct 30, 2000 | Issued |
Array
(
[id] => 1600347
[patent_doc_number] => 06475864
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Method of manufacturing a super-junction semiconductor device with an conductivity type layer'
[patent_app_type] => B1
[patent_app_number] => 09/694098
[patent_app_country] => US
[patent_app_date] => 2000-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 64
[patent_no_of_words] => 9921
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[pdf_file] => patents/06/475/06475864.pdf
[firstpage_image] =>[orig_patent_app_number] => 09694098
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/694098 | Method of manufacturing a super-junction semiconductor device with an conductivity type layer | Oct 22, 2000 | Issued |
Array
(
[id] => 1565811
[patent_doc_number] => 06376321
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Method of making a pn-junction in a semiconductor element'
[patent_app_type] => B1
[patent_app_number] => 09/690218
[patent_app_country] => US
[patent_app_date] => 2000-10-17
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2200
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[pdf_file] => patents/06/376/06376321.pdf
[firstpage_image] =>[orig_patent_app_number] => 09690218
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/690218 | Method of making a pn-junction in a semiconductor element | Oct 16, 2000 | Issued |
Array
(
[id] => 1595333
[patent_doc_number] => 06492194
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-10
[patent_title] => 'Method for the packaging of electronic components'
[patent_app_type] => B1
[patent_app_number] => 09/688358
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 09688358
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/688358 | Method for the packaging of electronic components | Oct 11, 2000 | Issued |
Array
(
[id] => 7643956
[patent_doc_number] => 06429082
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Method of manufacturing a high voltage using a latid process for forming a LDD'
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[patent_app_number] => 09/684118
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Array
(
[id] => 1595724
[patent_doc_number] => 06492263
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-10
[patent_title] => 'Dual damascene process which prevents diffusion of metals and improves trench-to-via alignment'
[patent_app_type] => B1
[patent_app_number] => 09/684038
[patent_app_country] => US
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Array
(
[id] => 7645713
[patent_doc_number] => 06472256
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[patent_issue_date] => 2002-10-29
[patent_title] => 'Method of manufacturing a thin-film transistor with a short-circuiting pattern'
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[patent_app_number] => 09/680368
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Array
(
[id] => 1532495
[patent_doc_number] => 06410397
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Method for manufacturing a dielectric trench capacitor with a stacked-layer structure'
[patent_app_type] => B1
[patent_app_number] => 09/677260
[patent_app_country] => US
[patent_app_date] => 2000-10-02
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/677260 | Method for manufacturing a dielectric trench capacitor with a stacked-layer structure | Oct 1, 2000 | Issued |
Array
(
[id] => 4395705
[patent_doc_number] => 06297168
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Edge defect inhibited trench etch plasma etch method'
[patent_app_type] => 1
[patent_app_number] => 9/677068
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/677068 | Edge defect inhibited trench etch plasma etch method | Sep 28, 2000 | Issued |
Array
(
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[patent_issue_date] => 2001-12-25
[patent_title] => 'Method for manufacturing semiconductor memory'
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[firstpage_image] =>[orig_patent_app_number] => 668308
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/668308 | Method for manufacturing semiconductor memory | Sep 24, 2000 | Issued |
Array
(
[id] => 4287383
[patent_doc_number] => 06268299
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[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Variable stoichiometry silicon nitride barrier films for tunable etch selectivity and enhanced hyrogen permeability'
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[patent_app_number] => 9/668988
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[firstpage_image] =>[orig_patent_app_number] => 668988
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/668988 | Variable stoichiometry silicon nitride barrier films for tunable etch selectivity and enhanced hyrogen permeability | Sep 24, 2000 | Issued |
Array
(
[id] => 1485267
[patent_doc_number] => 06365478
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[patent_issue_date] => 2002-04-02
[patent_title] => 'Solid state electronic device fabrication using crystalline defect control'
[patent_app_type] => B1
[patent_app_number] => 09/667988
[patent_app_country] => US
[patent_app_date] => 2000-09-22
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[pdf_file] => patents/06/365/06365478.pdf
[firstpage_image] =>[orig_patent_app_number] => 09667988
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/667988 | Solid state electronic device fabrication using crystalline defect control | Sep 21, 2000 | Issued |