Search

Thuan V. Do

Examiner (ID: 3444, Phone: (571)272-1891 , Office: P/2851 )

Most Active Art Unit
2825
Art Unit(s)
2763, 2851, 2825, 2768
Total Applications
1369
Issued Applications
1268
Pending Applications
16
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9714567 [patent_doc_number] => 08839170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Power/performance optimization through temperature/voltage control' [patent_app_type] => utility [patent_app_number] => 13/749851 [patent_app_country] => US [patent_app_date] => 2013-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 14478 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13749851 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/749851
Power/performance optimization through temperature/voltage control Jan 24, 2013 Issued
Array ( [id] => 9593012 [patent_doc_number] => 08782578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Generating interface adjustment signals in a device-to-device interconnection system' [patent_app_type] => utility [patent_app_number] => 13/747419 [patent_app_country] => US [patent_app_date] => 2013-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 19440 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13747419 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/747419
Generating interface adjustment signals in a device-to-device interconnection system Jan 21, 2013 Issued
Array ( [id] => 10624963 [patent_doc_number] => 09343918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Balancing apparatus, balancing method, and battery module' [patent_app_type] => utility [patent_app_number] => 13/743764 [patent_app_country] => US [patent_app_date] => 2013-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5178 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13743764 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/743764
Balancing apparatus, balancing method, and battery module Jan 16, 2013 Issued
Array ( [id] => 8925918 [patent_doc_number] => 20130181678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'COMPOSITIONS, LAYERINGS, ELECTRODES & METHODS FOR MAKING' [patent_app_type] => utility [patent_app_number] => 13/743868 [patent_app_country] => US [patent_app_date] => 2013-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 22077 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13743868 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/743868
Compositions, layerings, electrodes and methods for making Jan 16, 2013 Issued
Array ( [id] => 8925917 [patent_doc_number] => 20130181677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'COMPOSITIONS, LAYERINGS, ELECTRODES AND METHODS FOR MAKING' [patent_app_type] => utility [patent_app_number] => 13/743751 [patent_app_country] => US [patent_app_date] => 2013-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 19226 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13743751 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/743751
COMPOSITIONS, LAYERINGS, ELECTRODES AND METHODS FOR MAKING Jan 16, 2013 Abandoned
Array ( [id] => 11300597 [patent_doc_number] => 09508607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Thermal management of tightly integrated semiconductor device, system and/or package' [patent_app_type] => utility [patent_app_number] => 13/741755 [patent_app_country] => US [patent_app_date] => 2013-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12574 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741755 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/741755
Thermal management of tightly integrated semiconductor device, system and/or package Jan 14, 2013 Issued
Array ( [id] => 11614715 [patent_doc_number] => 09652572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Method and apparatus for performing logic synthesis' [patent_app_type] => utility [patent_app_number] => 14/758971 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3879 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14758971 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/758971
Method and apparatus for performing logic synthesis Jan 7, 2013 Issued
Array ( [id] => 10144279 [patent_doc_number] => 09177088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'Computer product for supporting design and verification of integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/730102 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 9791 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730102 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730102
Computer product for supporting design and verification of integrated circuit Dec 27, 2012 Issued
Array ( [id] => 9564054 [patent_doc_number] => 20140181767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'METHOD, APPARATUS, AND SYSTEM FOR EFFICIENT PRE-SILICON DEBUG' [patent_app_type] => utility [patent_app_number] => 13/721790 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6986 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721790 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721790
Method and apparatus for efficient pre-silicon debug Dec 19, 2012 Issued
Array ( [id] => 10562738 [patent_doc_number] => 09286416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Scanner based optical proximity correction system and method of use' [patent_app_type] => utility [patent_app_number] => 13/721910 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10649 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721910 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721910
Scanner based optical proximity correction system and method of use Dec 19, 2012 Issued
Array ( [id] => 10125961 [patent_doc_number] => 09160336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'System and method for critical path replication' [patent_app_type] => utility [patent_app_number] => 13/715721 [patent_app_country] => US [patent_app_date] => 2012-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7643 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13715721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/715721
System and method for critical path replication Dec 13, 2012 Issued
Array ( [id] => 9417025 [patent_doc_number] => 08701077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-15 [patent_title] => 'Individual ROM codes on a single reticle for a plurality of devices' [patent_app_type] => utility [patent_app_number] => 13/710291 [patent_app_country] => US [patent_app_date] => 2012-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2821 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13710291 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/710291
Individual ROM codes on a single reticle for a plurality of devices Dec 9, 2012 Issued
Array ( [id] => 10834859 [patent_doc_number] => 08863054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-14 [patent_title] => 'Innovative verification methodology for deeply embedded computational element' [patent_app_type] => utility [patent_app_number] => 13/693841 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693841 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/693841
Innovative verification methodology for deeply embedded computational element Dec 3, 2012 Issued
Array ( [id] => 10885703 [patent_doc_number] => 08910107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-09 [patent_title] => 'Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured space' [patent_app_type] => utility [patent_app_number] => 13/693011 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 16319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693011 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/693011
Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured space Dec 2, 2012 Issued
Array ( [id] => 10890749 [patent_doc_number] => 08914763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-16 [patent_title] => 'Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured space' [patent_app_type] => utility [patent_app_number] => 13/692970 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 16256 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13692970 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/692970
Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured space Dec 2, 2012 Issued
Array ( [id] => 11356954 [patent_doc_number] => 09533595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Vehicular battery system and vehicle equipped with same' [patent_app_type] => utility [patent_app_number] => 14/408566 [patent_app_country] => US [patent_app_date] => 2012-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6993 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14408566 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/408566
Vehicular battery system and vehicle equipped with same Nov 28, 2012 Issued
Array ( [id] => 8865933 [patent_doc_number] => 20130149636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'PATTERN DETERMINING METHOD, PATTERN DETERMINING APPARATUS AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 13/685791 [patent_app_country] => US [patent_app_date] => 2012-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10746 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685791 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/685791
Pattern determining method, pattern determining apparatus and storage medium Nov 26, 2012 Issued
Array ( [id] => 12944275 [patent_doc_number] => 09834100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Charge/discharge system [patent_app_type] => utility [patent_app_number] => 14/442156 [patent_app_country] => US [patent_app_date] => 2012-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5828 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14442156 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/442156
Charge/discharge system Nov 11, 2012 Issued
Array ( [id] => 9436710 [patent_doc_number] => 20140114617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'ADAPTIVE TEMPLATE SYSTEM FOR AN AUTOMATED PCB MANUFACTURING RELEASE PACKAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/654961 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 6046 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654961 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/654961
Adaptive template system for an automated PCB manufacturing release package system Oct 17, 2012 Issued
Array ( [id] => 10293430 [patent_doc_number] => 20150178429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'SOI MOS DEVICE MODELING METHOD' [patent_app_type] => utility [patent_app_number] => 14/415275 [patent_app_country] => US [patent_app_date] => 2012-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1872 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14415275 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/415275
SOI MOS device modeling method Sep 20, 2012 Issued
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