Tien Quang Dinh

Array ( [id] => 3033169 [patent_doc_number] => 05349223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'High current high voltage vertical PMOS in ultra high voltage CMOS' [patent_app_type] => 1 [patent_app_number] => 8/166400 [patent_app_country] => US [patent_app_date] => 1993-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1946 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349223.pdf [firstpage_image] =>[orig_patent_app_number] => 166400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3486941 [patent_doc_number] => 05446302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Integrated circuit with diode-connected transistor for reducing ESD damage' [patent_app_type] => 1 [patent_app_number] => 8/166636 [patent_app_country] => US [patent_app_date] => 1993-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2526 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446302.pdf [firstpage_image] =>[orig_patent_app_number] => 166636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3463579 [patent_doc_number] => 05382818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-17 [patent_title] => 'Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode' [patent_app_type] => 1 [patent_app_number] => 8/164230 [patent_app_country] => US [patent_app_date] => 1993-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2614 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/382/05382818.pdf [firstpage_image] =>[orig_patent_app_number] => 164230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4137244 [patent_doc_number] => 06034419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Semiconductor device with a tungsten contact' [patent_app_type] => 1 [patent_app_number] => 8/161604 [patent_app_country] => US [patent_app_date] => 1993-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4606 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034419.pdf [firstpage_image] =>[orig_patent_app_number] => 161604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3416683 [patent_doc_number] => 05453392 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Process for forming flat-cell mask ROMS' [patent_app_type] => 1 [patent_app_number] => 8/160246 [patent_app_country] => US [patent_app_date] => 1993-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 1847 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/453/05453392.pdf [firstpage_image] =>[orig_patent_app_number] => 160246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3561508 [patent_doc_number] => 05502315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Electrically programmable interconnect structure having a PECVD amorphous silicon element' [patent_app_type] => 1 [patent_app_number] => 8/161504 [patent_app_country] => US [patent_app_date] => 1993-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5678 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502315.pdf [firstpage_image] =>[orig_patent_app_number] => 161504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3454404 [patent_doc_number] => 05386134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Asymmetric electro-static discharge transistors for increased electro-static discharge hardness' [patent_app_type] => 1 [patent_app_number] => 8/156156 [patent_app_country] => US [patent_app_date] => 1993-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3105 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386134.pdf [firstpage_image] =>[orig_patent_app_number] => 156156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3571004 [patent_doc_number] => 05485031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Antifuse structure suitable for VLSI application' [patent_app_type] => 1 [patent_app_number] => 8/156612 [patent_app_country] => US [patent_app_date] => 1993-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4721 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485031.pdf [firstpage_image] =>[orig_patent_app_number] => 156612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3579821 [patent_doc_number] => 05523612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Method of manufacturing an antifuse with doped barrier metal layer and resulting antifuse' [patent_app_type] => 1 [patent_app_number] => 8/154842 [patent_app_country] => US [patent_app_date] => 1993-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1654 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/523/05523612.pdf [firstpage_image] =>[orig_patent_app_number] => 154842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3128532 [patent_doc_number] => 05436484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Semiconductor integrated circuit device having input protective elements and internal circuits' [patent_app_type] => 1 [patent_app_number] => 8/143151 [patent_app_country] => US [patent_app_date] => 1993-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 9151 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/436/05436484.pdf [firstpage_image] =>[orig_patent_app_number] => 143151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3128517 [patent_doc_number] => 05436483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Semiconductor integrated circuit device having a first MISFET of an output buffer circuit and a second MISFET of an internal circuit' [patent_app_type] => 1 [patent_app_number] => 8/142965 [patent_app_country] => US [patent_app_date] => 1993-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 9151 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/436/05436483.pdf [firstpage_image] =>[orig_patent_app_number] => 142965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3444335 [patent_doc_number] => 05397715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'MOS transistor having increased gate-drain capacitance' [patent_app_type] => 1 [patent_app_number] => 8/140746 [patent_app_country] => US [patent_app_date] => 1993-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2111 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/397/05397715.pdf [firstpage_image] =>[orig_patent_app_number] => 140746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3699876 [patent_doc_number] => 05596218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Hot carrier-hard gate oxides by nitrogen implantation before gate oxidation' [patent_app_type] => 1 [patent_app_number] => 8/138906 [patent_app_country] => US [patent_app_date] => 1993-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2789 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596218.pdf [firstpage_image] =>[orig_patent_app_number] => 138906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3119104 [patent_doc_number] => 05410162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Apparatus for and method of rapid testing of semiconductor components at elevated temperature' [patent_app_type] => 1 [patent_app_number] => 8/137662 [patent_app_country] => US [patent_app_date] => 1993-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2359 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410162.pdf [firstpage_image] =>[orig_patent_app_number] => 137662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3043295 [patent_doc_number] => 05376815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Semiconductor device having bipolar-mos composite element pellet suitable for pressure contacted structure' [patent_app_type] => 1 [patent_app_number] => 8/123988 [patent_app_country] => US [patent_app_date] => 1993-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 40 [patent_no_of_words] => 7237 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/376/05376815.pdf [firstpage_image] =>[orig_patent_app_number] => 123988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3420254 [patent_doc_number] => 05394007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Isolated well and method of making' [patent_app_type] => 1 [patent_app_number] => 8/119636 [patent_app_country] => US [patent_app_date] => 1993-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2586 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/394/05394007.pdf [firstpage_image] =>[orig_patent_app_number] => 119636 [rel_patent_id] =>[rel_patent_doc_number] =>)