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Tien Quang Dinh

Supervisory Patent Examiner (ID: 8179, Phone: (571)272-6899 , Office: P/3647 )

Most Active Art Unit
3644
Art Unit(s)
3104, 3647, 3641, 3644, 3613
Total Applications
1457
Issued Applications
1028
Pending Applications
118
Abandoned Applications
313

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3606931 [patent_doc_number] => 05578866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Method of manufacturing a block-shaped support body for a semiconductor component' [patent_app_type] => 1 [patent_app_number] => 8/115335 [patent_app_country] => US [patent_app_date] => 1993-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3294 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/578/05578866.pdf [firstpage_image] =>[orig_patent_app_number] => 115335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/115335
Method of manufacturing a block-shaped support body for a semiconductor component Aug 31, 1993 Issued
08/113250 PHASE SHIFTING MASK AND METHOD OF MANUFACTURING SAME Aug 29, 1993 Abandoned
Array ( [id] => 4002781 [patent_doc_number] => 05986315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Guard wall to reduce delamination effects within a semiconductor die' [patent_app_type] => 1 [patent_app_number] => 8/112445 [patent_app_country] => US [patent_app_date] => 1993-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 5043 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986315.pdf [firstpage_image] =>[orig_patent_app_number] => 112445 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/112445
Guard wall to reduce delamination effects within a semiconductor die Aug 25, 1993 Issued
Array ( [id] => 3483936 [patent_doc_number] => 05399893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Diode protected semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/111326 [patent_app_country] => US [patent_app_date] => 1993-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2445 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399893.pdf [firstpage_image] =>[orig_patent_app_number] => 111326 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/111326
Diode protected semiconductor device Aug 23, 1993 Issued
08/110194 SEMICONDUCTOR DEVICE CONTAINING ELECTROSTATIC CAPACITIVE ELEMENT AND METHOD FOR MANUFACTURING SAME Aug 22, 1993 Abandoned
Array ( [id] => 3490854 [patent_doc_number] => 05426322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Diodes for electrostatic discharge protection and voltage references' [patent_app_type] => 1 [patent_app_number] => 8/093074 [patent_app_country] => US [patent_app_date] => 1993-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 34 [patent_no_of_words] => 6671 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426322.pdf [firstpage_image] =>[orig_patent_app_number] => 093074 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/093074
Diodes for electrostatic discharge protection and voltage references Aug 19, 1993 Issued
Array ( [id] => 3594209 [patent_doc_number] => 05585661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Sub-micron bonded SOI by trench planarization' [patent_app_type] => 1 [patent_app_number] => 8/108358 [patent_app_country] => US [patent_app_date] => 1993-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 8 [patent_no_of_words] => 2165 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/585/05585661.pdf [firstpage_image] =>[orig_patent_app_number] => 108358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/108358
Sub-micron bonded SOI by trench planarization Aug 17, 1993 Issued
Array ( [id] => 3040992 [patent_doc_number] => 05373179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-13 [patent_title] => 'Protective device for semiconductor IC' [patent_app_type] => 1 [patent_app_number] => 8/103094 [patent_app_country] => US [patent_app_date] => 1993-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3810 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/373/05373179.pdf [firstpage_image] =>[orig_patent_app_number] => 103094 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/103094
Protective device for semiconductor IC Aug 5, 1993 Issued
08/100631 CHIP DECOUPLING CAPACITOR Jul 28, 1993 Pending
Array ( [id] => 3077343 [patent_doc_number] => 05365110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-15 [patent_title] => 'Semiconductor device with multi-layered wiring structure' [patent_app_type] => 1 [patent_app_number] => 8/096844 [patent_app_country] => US [patent_app_date] => 1993-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2208 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/365/05365110.pdf [firstpage_image] =>[orig_patent_app_number] => 096844 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/096844
Semiconductor device with multi-layered wiring structure Jul 25, 1993 Issued
Array ( [id] => 3100412 [patent_doc_number] => 05298786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'SOI lateral bipolar transistor with edge-strapped base contact and method of fabricating same' [patent_app_type] => 1 [patent_app_number] => 8/093515 [patent_app_country] => US [patent_app_date] => 1993-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 2734 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/298/05298786.pdf [firstpage_image] =>[orig_patent_app_number] => 093515 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/093515
SOI lateral bipolar transistor with edge-strapped base contact and method of fabricating same Jul 18, 1993 Issued
08/092682 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME Jul 15, 1993 Pending
Array ( [id] => 3121002 [patent_doc_number] => 05449947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Read-disturb tolerant metal-to-metal antifuse and fabrication method' [patent_app_type] => 1 [patent_app_number] => 8/088298 [patent_app_country] => US [patent_app_date] => 1993-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 7049 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/449/05449947.pdf [firstpage_image] =>[orig_patent_app_number] => 088298 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/088298
Read-disturb tolerant metal-to-metal antifuse and fabrication method Jul 6, 1993 Issued
Array ( [id] => 3415599 [patent_doc_number] => 05393702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Via sidewall SOG nitridation for via filling' [patent_app_type] => 1 [patent_app_number] => 8/085955 [patent_app_country] => US [patent_app_date] => 1993-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1726 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/393/05393702.pdf [firstpage_image] =>[orig_patent_app_number] => 085955 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/085955
Via sidewall SOG nitridation for via filling Jul 5, 1993 Issued
Array ( [id] => 3002841 [patent_doc_number] => 05359221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/086096 [patent_app_country] => US [patent_app_date] => 1993-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 33 [patent_no_of_words] => 7642 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359221.pdf [firstpage_image] =>[orig_patent_app_number] => 086096 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/086096
Semiconductor device Jul 5, 1993 Issued
08/086976 TRENCH DMOS POWER TRANSISTOR WITH FIELD-SHAPING BODY PROFILE AND THREE-DIMENSIONAL GEOMETRY Jul 1, 1993 Pending
08/084948 DIELECTRIC ELEMENT ISOLATED SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME Jul 1, 1993 Pending
08/084604 SEMICONDUCTOR DEVICE Jun 30, 1993 Pending
08/083277 MIXED TECHNOLOGY INTEGRATED DEVICE COMPRISING COMPLEMENTARY LDMOS POWER TRANSISTORS, CMOS AND VERTICAL PNP INTEGRATED STRUCTURES HAVING AN ENHANCED ABILITY TO WITHSTAND A RELATIVELY HIGH SUPPLY VOLTAGE Jun 27, 1993 Pending
Array ( [id] => 3480038 [patent_doc_number] => 05432368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Pad protection diode structure' [patent_app_type] => 1 [patent_app_number] => 8/082236 [patent_app_country] => US [patent_app_date] => 1993-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1942 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432368.pdf [firstpage_image] =>[orig_patent_app_number] => 082236 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/082236
Pad protection diode structure Jun 23, 1993 Issued
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