| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2966921
[patent_doc_number] => 05274262
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-28
[patent_title] => 'SCR protection structure and circuit with reduced trigger voltage'
[patent_app_type] => 1
[patent_app_number] => 7/803880
[patent_app_country] => US
[patent_app_date] => 1991-12-09
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/274/05274262.pdf
[firstpage_image] =>[orig_patent_app_number] => 803880
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/803880 | SCR protection structure and circuit with reduced trigger voltage | Dec 8, 1991 | Issued |
| 90/002515 | HIGH POWER MOSFET WITH LOW ON-RESISTANCE AND HIGH BREAKDOWN VOLTAGE | Nov 12, 1991 | Issued |
Array
(
[id] => 2850791
[patent_doc_number] => 05138401
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-11
[patent_title] => 'Electronic devices utilizing superconducting materials'
[patent_app_type] => 1
[patent_app_number] => 7/780441
[patent_app_country] => US
[patent_app_date] => 1991-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/138/05138401.pdf
[firstpage_image] =>[orig_patent_app_number] => 780441
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/780441 | Electronic devices utilizing superconducting materials | Oct 16, 1991 | Issued |
| 90/002478 | PLURAL POLYGON SOURCE PATTERN FOR MOSFET | Oct 8, 1991 | Issued |
Array
(
[id] => 2948964
[patent_doc_number] => 05254874
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-19
[patent_title] => 'High density local interconnect in a semiconductor circuit using metal silicide'
[patent_app_type] => 1
[patent_app_number] => 7/773972
[patent_app_country] => US
[patent_app_date] => 1991-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2693
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[patent_words_short_claim] => 106
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[pdf_file] => patents/05/254/05254874.pdf
[firstpage_image] =>[orig_patent_app_number] => 773972
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/773972 | High density local interconnect in a semiconductor circuit using metal silicide | Oct 7, 1991 | Issued |
| 07/755406 | A VERTICAL DMOS TRANSISTOR STRUCTURE BUILT IN AN N-WELL CMOS-BASED BICMOS PROCESS | Sep 4, 1991 | Abandoned |
Array
(
[id] => 2901755
[patent_doc_number] => 05177582
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-05
[patent_title] => 'CMOS-compatible bipolar transistor with reduced collector/substrate capacitance and process for producing the same'
[patent_app_type] => 1
[patent_app_number] => 7/754377
[patent_app_country] => US
[patent_app_date] => 1991-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 7342
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[pdf_file] => patents/05/177/05177582.pdf
[firstpage_image] =>[orig_patent_app_number] => 754377
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/754377 | CMOS-compatible bipolar transistor with reduced collector/substrate capacitance and process for producing the same | Aug 29, 1991 | Issued |
Array
(
[id] => 3447050
[patent_doc_number] => 05466960
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => 'BiCMOS device having self-aligned well tap and method of fabrication'
[patent_app_type] => 1
[patent_app_number] => 7/753272
[patent_app_country] => US
[patent_app_date] => 1991-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => patents/05/466/05466960.pdf
[firstpage_image] =>[orig_patent_app_number] => 753272
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/753272 | BiCMOS device having self-aligned well tap and method of fabrication | Aug 19, 1991 | Issued |
Array
(
[id] => 2792232
[patent_doc_number] => 05142345
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-25
[patent_title] => 'Structure of input protection transistor in semiconductor device including memory transistor having double-layered gate and method of manufacturing semiconductor device including such input protection transistor'
[patent_app_type] => 1
[patent_app_number] => 7/746187
[patent_app_country] => US
[patent_app_date] => 1991-08-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/142/05142345.pdf
[firstpage_image] =>[orig_patent_app_number] => 746187
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/746187 | Structure of input protection transistor in semiconductor device including memory transistor having double-layered gate and method of manufacturing semiconductor device including such input protection transistor | Aug 14, 1991 | Issued |
| 07/744823 | SUPERCONDUCTING DEVICE | Aug 11, 1991 | Abandoned |
Array
(
[id] => 2967586
[patent_doc_number] => 05198881
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-30
[patent_title] => 'Barrier layer device processing'
[patent_app_type] => 1
[patent_app_number] => 7/742274
[patent_app_country] => US
[patent_app_date] => 1991-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/198/05198881.pdf
[firstpage_image] =>[orig_patent_app_number] => 742274
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/742274 | Barrier layer device processing | Aug 6, 1991 | Issued |
Array
(
[id] => 3092708
[patent_doc_number] => 05278436
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-11
[patent_title] => 'Semiconductor integrated circuit device for forming logic circuit including resistance element connected to bipolar transistor with smaller occupied area'
[patent_app_type] => 1
[patent_app_number] => 7/739144
[patent_app_country] => US
[patent_app_date] => 1991-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 3692
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[pdf_file] => patents/05/278/05278436.pdf
[firstpage_image] =>[orig_patent_app_number] => 739144
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/739144 | Semiconductor integrated circuit device for forming logic circuit including resistance element connected to bipolar transistor with smaller occupied area | Jul 31, 1991 | Issued |
| 07/739381 | SEMICONDUCTOR DEVICE WITH TUNGSTEN CONTACT | Jul 31, 1991 | Abandoned |
Array
(
[id] => 2902912
[patent_doc_number] => 05184202
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-02
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 7/737238
[patent_app_country] => US
[patent_app_date] => 1991-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/184/05184202.pdf
[firstpage_image] =>[orig_patent_app_number] => 737238
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/737238 | Semiconductor integrated circuit device | Jul 28, 1991 | Issued |
| 07/735504 | METHOD OF FORMING A PLANARIZED INSULATION LAYER | Jul 24, 1991 | Abandoned |
Array
(
[id] => 2795715
[patent_doc_number] => 05101262
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-31
[patent_title] => 'Semiconductor memory device and method of manufacturing it'
[patent_app_type] => 1
[patent_app_number] => 7/737603
[patent_app_country] => US
[patent_app_date] => 1991-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/05/101/05101262.pdf
[firstpage_image] =>[orig_patent_app_number] => 737603
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/737603 | Semiconductor memory device and method of manufacturing it | Jul 24, 1991 | Issued |
Array
(
[id] => 2973598
[patent_doc_number] => 05258643
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-02
[patent_title] => 'Electrically programmable link structures and methods of making same'
[patent_app_type] => 1
[patent_app_number] => 7/735427
[patent_app_country] => US
[patent_app_date] => 1991-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[firstpage_image] =>[orig_patent_app_number] => 735427
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/735427 | Electrically programmable link structures and methods of making same | Jul 24, 1991 | Issued |
Array
(
[id] => 2856739
[patent_doc_number] => 05105242
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-14
[patent_title] => 'Field effect transistor having Schottky contact and a high frequency characteristic'
[patent_app_type] => 1
[patent_app_number] => 7/732437
[patent_app_country] => US
[patent_app_date] => 1991-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/105/05105242.pdf
[firstpage_image] =>[orig_patent_app_number] => 732437
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/732437 | Field effect transistor having Schottky contact and a high frequency characteristic | Jul 17, 1991 | Issued |
| 07/714796 | REACTIVE ION ETCHING BUFFER MASK | Jul 15, 1991 | Abandoned |
Array
(
[id] => 2803485
[patent_doc_number] => 05144408
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-01
[patent_title] => 'Semiconductor integrated circuit device and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 7/730518
[patent_app_country] => US
[patent_app_date] => 1991-07-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/144/05144408.pdf
[firstpage_image] =>[orig_patent_app_number] => 730518
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/730518 | Semiconductor integrated circuit device and method of manufacturing the same | Jul 11, 1991 | Issued |