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Tien Quang Dinh

Supervisory Patent Examiner (ID: 8179, Phone: (571)272-6899 , Office: P/3647 )

Most Active Art Unit
3644
Art Unit(s)
3104, 3647, 3641, 3644, 3613
Total Applications
1457
Issued Applications
1028
Pending Applications
118
Abandoned Applications
313

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2834042 [patent_doc_number] => 05117271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-26 [patent_title] => 'Low capacitance bipolar junction transistor and fabrication process therfor' [patent_app_type] => 1 [patent_app_number] => 7/624018 [patent_app_country] => US [patent_app_date] => 1990-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/117/05117271.pdf [firstpage_image] =>[orig_patent_app_number] => 624018 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/624018
Low capacitance bipolar junction transistor and fabrication process therfor Dec 6, 1990 Issued
07/624402 SEMICONDUCTOR DEVICE OF MOS STRUCTURE HAVING P-TYPE GATE ELECTRODE Dec 6, 1990 Abandoned
07/622986 AN SOI LATERAL BIPOLAR TRANSISTOR WITH EDGE-STRAPPED BASE CONTACT AND METHOD OF FABRICATING SAME Dec 5, 1990 Abandoned
07/623876 BIPOLAR ESD PROTECTION FOR INTEGRATED CIRCUITS Dec 3, 1990 Abandoned
Array ( [id] => 2756008 [patent_doc_number] => 05031010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-09 [patent_title] => 'Semiconductor memory device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 7/622148 [patent_app_country] => US [patent_app_date] => 1990-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 4103 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/031/05031010.pdf [firstpage_image] =>[orig_patent_app_number] => 622148 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/622148
Semiconductor memory device and method of manufacturing the same Dec 2, 1990 Issued
Array ( [id] => 2879400 [patent_doc_number] => 05091759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-25 [patent_title] => 'Heterostructure field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/618005 [patent_app_country] => US [patent_app_date] => 1990-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3352 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/091/05091759.pdf [firstpage_image] =>[orig_patent_app_number] => 618005 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/618005
Heterostructure field effect transistor Nov 25, 1990 Issued
07/617795 A SEMICONDUCTOR DEVICE HAVING AN INTERNAL CELL ARRAY REGION AND A PERIPHERAL REGION SURROUNDING THR INTERNAL CELL ARRAY FOR PROVIDING INPUT/OUTPUT BASIC CELLS Nov 25, 1990 Abandoned
Array ( [id] => 3732369 [patent_doc_number] => 05652449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Semiconductor device with an insulating film separating conductive layers and method of maufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/617251 [patent_app_country] => US [patent_app_date] => 1990-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2031 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652449.pdf [firstpage_image] =>[orig_patent_app_number] => 617251 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/617251
Semiconductor device with an insulating film separating conductive layers and method of maufacturing semiconductor device Nov 22, 1990 Issued
Array ( [id] => 2783504 [patent_doc_number] => 05151770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-29 [patent_title] => 'Shielded semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/616366 [patent_app_country] => US [patent_app_date] => 1990-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5126 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/151/05151770.pdf [firstpage_image] =>[orig_patent_app_number] => 616366 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/616366
Shielded semiconductor device Nov 20, 1990 Issued
07/619651 METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Nov 18, 1990 Abandoned
Array ( [id] => 2803522 [patent_doc_number] => 05144409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'Isotopically enriched semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/615425 [patent_app_country] => US [patent_app_date] => 1990-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3059 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/144/05144409.pdf [firstpage_image] =>[orig_patent_app_number] => 615425 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/615425
Isotopically enriched semiconductor devices Nov 15, 1990 Issued
07/612972 SEMICONDUCTOR DEVICE HAVING BIPOLAR-MOS COMPOSITE ELEMENT PELLET SUITABLE FOR PRESSURE CONTACTED STRUCTURE Nov 14, 1990 Abandoned
07/612676 COMPLEMENTARY SEMICONDUCTOR DEVICE USING DIAMOND THIN FILM AND THE METHOD OF MANUFACTURING THIS DEVICE Nov 13, 1990 Abandoned
Array ( [id] => 2677642 [patent_doc_number] => 05034798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-23 [patent_title] => 'Semiconductor device having a two-layer gate structure' [patent_app_type] => 1 [patent_app_number] => 7/612466 [patent_app_country] => US [patent_app_date] => 1990-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3179 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/034/05034798.pdf [firstpage_image] =>[orig_patent_app_number] => 612466 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/612466
Semiconductor device having a two-layer gate structure Nov 13, 1990 Issued
07/611482 NONVOLATILE SEMICONDUCTOR MEMORY AND A METHOD OF MANUFACTURING THE SAME Nov 8, 1990 Abandoned
Array ( [id] => 2731469 [patent_doc_number] => 05057882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Thermally optimized interdigitated transistor' [patent_app_type] => 1 [patent_app_number] => 7/611393 [patent_app_country] => US [patent_app_date] => 1990-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3229 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/057/05057882.pdf [firstpage_image] =>[orig_patent_app_number] => 611393 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/611393
Thermally optimized interdigitated transistor Nov 4, 1990 Issued
07/608344 SEMICONDUCTOR DEVICE WITH MULTI-LAYERED WIRING STRUCTURE Nov 1, 1990 Abandoned
Array ( [id] => 2900192 [patent_doc_number] => 05210596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Thermally optimized interdigitated transistor' [patent_app_type] => 1 [patent_app_number] => 7/608119 [patent_app_country] => US [patent_app_date] => 1990-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3223 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210596.pdf [firstpage_image] =>[orig_patent_app_number] => 608119 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/608119
Thermally optimized interdigitated transistor Oct 31, 1990 Issued
Array ( [id] => 2851222 [patent_doc_number] => 05138424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-11 [patent_title] => 'Positive working polyamic acid/imide photoresist compositions and their use as dielectrics' [patent_app_type] => 1 [patent_app_number] => 7/606460 [patent_app_country] => US [patent_app_date] => 1990-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5601 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/138/05138424.pdf [firstpage_image] =>[orig_patent_app_number] => 606460 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/606460
Positive working polyamic acid/imide photoresist compositions and their use as dielectrics Oct 30, 1990 Issued
07/606658 SELF-ALIGNED EPITAXIAL BASE TRANSISTOR AND METHOD FOR FABRICATING SAME Oct 30, 1990 Abandoned
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