| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2851148
[patent_doc_number] => 05138420
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-11
[patent_title] => 'Semiconductor device having first and second type field effect transistors separated by a barrier'
[patent_app_type] => 1
[patent_app_number] => 7/608050
[patent_app_country] => US
[patent_app_date] => 1990-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 39
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/138/05138420.pdf
[firstpage_image] =>[orig_patent_app_number] => 608050
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/608050 | Semiconductor device having first and second type field effect transistors separated by a barrier | Oct 30, 1990 | Issued |
Array
(
[id] => 2900228
[patent_doc_number] => 05210598
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-11
[patent_title] => 'Semiconductor element having a resistance state transition region of two-layer structure'
[patent_app_type] => 1
[patent_app_number] => 7/609109
[patent_app_country] => US
[patent_app_date] => 1990-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4022
[patent_no_of_claims] => 8
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[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/210/05210598.pdf
[firstpage_image] =>[orig_patent_app_number] => 609109
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/609109 | Semiconductor element having a resistance state transition region of two-layer structure | Oct 30, 1990 | Issued |
Array
(
[id] => 2731376
[patent_doc_number] => 05057877
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-15
[patent_title] => 'Superconductor interconnection apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/602898
[patent_app_country] => US
[patent_app_date] => 1990-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2596
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/057/05057877.pdf
[firstpage_image] =>[orig_patent_app_number] => 602898
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/602898 | Superconductor interconnection apparatus | Oct 25, 1990 | Issued |
| 07/603976 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE | Oct 22, 1990 | Abandoned |
Array
(
[id] => 2855788
[patent_doc_number] => 05111274
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-05-05
[patent_title] => 'Semiconductor integrated circuit with circuit blocks, dummy islands, and bias and shield electrodes'
[patent_app_type] => 1
[patent_app_number] => 7/602184
[patent_app_country] => US
[patent_app_date] => 1990-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 5842
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/111/05111274.pdf
[firstpage_image] =>[orig_patent_app_number] => 602184
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/602184 | Semiconductor integrated circuit with circuit blocks, dummy islands, and bias and shield electrodes | Oct 22, 1990 | Issued |
Array
(
[id] => 2851020
[patent_doc_number] => 05138413
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-11
[patent_title] => 'Piso electrostatic discharge protection device'
[patent_app_type] => 1
[patent_app_number] => 7/601974
[patent_app_country] => US
[patent_app_date] => 1990-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 3542
[patent_no_of_claims] => 12
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/138/05138413.pdf
[firstpage_image] =>[orig_patent_app_number] => 601974
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/601974 | Piso electrostatic discharge protection device | Oct 21, 1990 | Issued |
Array
(
[id] => 2828556
[patent_doc_number] => 05168366
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-01
[patent_title] => 'Dynamic semiconductor memory device comprising a switching transistor and storage capacitor'
[patent_app_type] => 1
[patent_app_number] => 7/600247
[patent_app_country] => US
[patent_app_date] => 1990-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1919
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/168/05168366.pdf
[firstpage_image] =>[orig_patent_app_number] => 600247
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/600247 | Dynamic semiconductor memory device comprising a switching transistor and storage capacitor | Oct 21, 1990 | Issued |
Array
(
[id] => 2807387
[patent_doc_number] => 05140391
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-18
[patent_title] => 'Thin film MOS transistor having pair of gate electrodes opposing across semiconductor layer'
[patent_app_type] => 1
[patent_app_number] => 7/601003
[patent_app_country] => US
[patent_app_date] => 1990-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2284
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 245
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/140/05140391.pdf
[firstpage_image] =>[orig_patent_app_number] => 601003
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/601003 | Thin film MOS transistor having pair of gate electrodes opposing across semiconductor layer | Oct 18, 1990 | Issued |
| 07/597698 | A SEMICONDUCTOR DEVICE HAVING A SHIELD WHICH IS MAINTANIED AT A REFERENCE POTENIAL | Oct 9, 1990 | Abandoned |
Array
(
[id] => 2689543
[patent_doc_number] => 05045913
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-03
[patent_title] => 'Bit stack compatible input/output circuits'
[patent_app_type] => 1
[patent_app_number] => 7/592764
[patent_app_country] => US
[patent_app_date] => 1990-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 3665
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/045/05045913.pdf
[firstpage_image] =>[orig_patent_app_number] => 592764
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/592764 | Bit stack compatible input/output circuits | Oct 3, 1990 | Issued |
| 07/586692 | CMOS-COMPATIBLE BIPOLAR TRANSISTOR WITH REDUCED COLLECTOR/SUBSTRATE CAPACITANCE AND PROCESS FOR PRODUCING THE SAME | Sep 23, 1990 | Abandoned |
Array
(
[id] => 2837601
[patent_doc_number] => 05128741
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-07
[patent_title] => 'Methods producing on a semi-conductor substructure a bipolar transistor, or a bipolar and a field effect transistor or a bipolar and a field effect transistor with a complementary field effect transistor and devices resulting from the methods'
[patent_app_type] => 1
[patent_app_number] => 7/585644
[patent_app_country] => US
[patent_app_date] => 1990-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 4405
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/128/05128741.pdf
[firstpage_image] =>[orig_patent_app_number] => 585644
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/585644 | Methods producing on a semi-conductor substructure a bipolar transistor, or a bipolar and a field effect transistor or a bipolar and a field effect transistor with a complementary field effect transistor and devices resulting from the methods | Sep 19, 1990 | Issued |
| 07/577526 | ISOTOPICALLY ENRICHED SILICON DEVICES | Sep 4, 1990 | Abandoned |
Array
(
[id] => 2803402
[patent_doc_number] => 05144404
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-01
[patent_title] => 'Polysilicon Schottky clamped transistor and vertical fuse devices'
[patent_app_type] => 1
[patent_app_number] => 7/571346
[patent_app_country] => US
[patent_app_date] => 1990-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4858
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/144/05144404.pdf
[firstpage_image] =>[orig_patent_app_number] => 571346
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/571346 | Polysilicon Schottky clamped transistor and vertical fuse devices | Aug 21, 1990 | Issued |
Array
(
[id] => 2687250
[patent_doc_number] => 05066998
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-19
[patent_title] => 'Severable conductive path in an integrated-circuit device'
[patent_app_type] => 1
[patent_app_number] => 7/569755
[patent_app_country] => US
[patent_app_date] => 1990-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/066/05066998.pdf
[firstpage_image] =>[orig_patent_app_number] => 569755
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/569755 | Severable conductive path in an integrated-circuit device | Aug 19, 1990 | Issued |
Array
(
[id] => 2830132
[patent_doc_number] => 05095357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-10
[patent_title] => 'Inductive structures for semiconductor integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 7/567170
[patent_app_country] => US
[patent_app_date] => 1990-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 40
[patent_no_of_words] => 6919
[patent_no_of_claims] => 28
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/095/05095357.pdf
[firstpage_image] =>[orig_patent_app_number] => 567170
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/567170 | Inductive structures for semiconductor integrated circuits | Aug 13, 1990 | Issued |
| 07/564705 | INTEGRATED SEMICONDUCTOR STRUCTURE WITH INCORPORATED ALIGNMENT MARKINGS | Aug 8, 1990 | Abandoned |
Array
(
[id] => 2715510
[patent_doc_number] => 05061980
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-29
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 7/564594
[patent_app_country] => US
[patent_app_date] => 1990-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 9962
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/061/05061980.pdf
[firstpage_image] =>[orig_patent_app_number] => 564594
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/564594 | Semiconductor integrated circuit device | Aug 8, 1990 | Issued |
Array
(
[id] => 2862173
[patent_doc_number] => 05113230
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-05-12
[patent_title] => 'Semiconductor device having a conductive layer for preventing insulation layer destruction'
[patent_app_type] => 1
[patent_app_number] => 7/565215
[patent_app_country] => US
[patent_app_date] => 1990-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 4110
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/113/05113230.pdf
[firstpage_image] =>[orig_patent_app_number] => 565215
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/565215 | Semiconductor device having a conductive layer for preventing insulation layer destruction | Aug 7, 1990 | Issued |
Array
(
[id] => 2867822
[patent_doc_number] => 05083184
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-21
[patent_title] => 'Capacitance device'
[patent_app_type] => 1
[patent_app_number] => 7/564250
[patent_app_country] => US
[patent_app_date] => 1990-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2726
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/083/05083184.pdf
[firstpage_image] =>[orig_patent_app_number] => 564250
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/564250 | Capacitance device | Aug 7, 1990 | Issued |