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Tien Quang Dinh

Supervisory Patent Examiner (ID: 8179, Phone: (571)272-6899 , Office: P/3647 )

Most Active Art Unit
3644
Art Unit(s)
3104, 3647, 3641, 3644, 3613
Total Applications
1457
Issued Applications
1028
Pending Applications
118
Abandoned Applications
313

Applications

Application numberTitle of the applicationFiling DateStatus
07/564685 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME Aug 2, 1990 Abandoned
Array ( [id] => 2752511 [patent_doc_number] => 05003375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-26 [patent_title] => 'MIS type semiconductor integrated circuit device having a refractory metal gate electrode and refractory metal silicide film covering the gate electrode' [patent_app_type] => 1 [patent_app_number] => 7/560006 [patent_app_country] => US [patent_app_date] => 1990-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3223 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/003/05003375.pdf [firstpage_image] =>[orig_patent_app_number] => 560006 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/560006
MIS type semiconductor integrated circuit device having a refractory metal gate electrode and refractory metal silicide film covering the gate electrode Jul 26, 1990 Issued
07/557782 COMPOUND SEMICONDUCTOR PELLET, AND METHOD FOR DICING COMPOUND SEMICON- DUCTOR WAFER Jul 25, 1990 Abandoned
Array ( [id] => 2729261 [patent_doc_number] => 05025300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-18 [patent_title] => 'Integrated circuits having improved fusible links' [patent_app_type] => 1 [patent_app_number] => 7/560462 [patent_app_country] => US [patent_app_date] => 1990-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2408 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/025/05025300.pdf [firstpage_image] =>[orig_patent_app_number] => 560462 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/560462
Integrated circuits having improved fusible links Jul 24, 1990 Issued
Array ( [id] => 2888105 [patent_doc_number] => 05109264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Semiconductor wafers having a shape suitable for thermal treatment' [patent_app_type] => 1 [patent_app_number] => 7/554406 [patent_app_country] => US [patent_app_date] => 1990-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 6460 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109264.pdf [firstpage_image] =>[orig_patent_app_number] => 554406 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/554406
Semiconductor wafers having a shape suitable for thermal treatment Jul 18, 1990 Issued
Array ( [id] => 2714390 [patent_doc_number] => 05068756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-26 [patent_title] => 'Integrated circuit composed of group III-V compound field effect and bipolar semiconductors' [patent_app_type] => 1 [patent_app_number] => 7/554116 [patent_app_country] => US [patent_app_date] => 1990-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 68 [patent_no_of_words] => 13535 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/068/05068756.pdf [firstpage_image] =>[orig_patent_app_number] => 554116 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/554116
Integrated circuit composed of group III-V compound field effect and bipolar semiconductors Jul 17, 1990 Issued
Array ( [id] => 2716666 [patent_doc_number] => 05041888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-20 [patent_title] => 'Insulator structure for amorphous silicon thin-film transistors' [patent_app_type] => 1 [patent_app_number] => 7/552977 [patent_app_country] => US [patent_app_date] => 1990-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5090 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/041/05041888.pdf [firstpage_image] =>[orig_patent_app_number] => 552977 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/552977
Insulator structure for amorphous silicon thin-film transistors Jul 15, 1990 Issued
Array ( [id] => 2676857 [patent_doc_number] => 05047819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-10 [patent_title] => 'Amorphous-silicon thin film transistor array substrate' [patent_app_type] => 1 [patent_app_number] => 7/551688 [patent_app_country] => US [patent_app_date] => 1990-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1766 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/047/05047819.pdf [firstpage_image] =>[orig_patent_app_number] => 551688 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/551688
Amorphous-silicon thin film transistor array substrate Jul 11, 1990 Issued
Array ( [id] => 2859470 [patent_doc_number] => 05089871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-18 [patent_title] => 'Increased voltage MOS semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/547828 [patent_app_country] => US [patent_app_date] => 1990-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2297 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/089/05089871.pdf [firstpage_image] =>[orig_patent_app_number] => 547828 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/547828
Increased voltage MOS semiconductor device Jul 2, 1990 Issued
Array ( [id] => 2677372 [patent_doc_number] => 05073814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Multi-sublayer dielectric layers' [patent_app_type] => 1 [patent_app_number] => 7/546960 [patent_app_country] => US [patent_app_date] => 1990-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7285 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073814.pdf [firstpage_image] =>[orig_patent_app_number] => 546960 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/546960
Multi-sublayer dielectric layers Jul 1, 1990 Issued
07/545149 ELECTRONIC DEVICES UTILIZING SUPERCONDUCTING MATERIALS Jun 26, 1990 Abandoned
Array ( [id] => 2752348 [patent_doc_number] => 05003366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-26 [patent_title] => 'Hetero-junction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/542796 [patent_app_country] => US [patent_app_date] => 1990-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2568 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/003/05003366.pdf [firstpage_image] =>[orig_patent_app_number] => 542796 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/542796
Hetero-junction bipolar transistor Jun 24, 1990 Issued
Array ( [id] => 2855773 [patent_doc_number] => 05111273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Fabrication of personalizable integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/540343 [patent_app_country] => US [patent_app_date] => 1990-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 3910 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/111/05111273.pdf [firstpage_image] =>[orig_patent_app_number] => 540343 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/540343
Fabrication of personalizable integrated circuits Jun 18, 1990 Issued
07/536130 WAFER-SCALE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF FORMING INTERCONNECTION LINES ARRANGED BETWEEN CHIPS OF WAFER-SCALE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Jun 10, 1990 Abandoned
Array ( [id] => 2716799 [patent_doc_number] => 05041895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-20 [patent_title] => 'Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage' [patent_app_type] => 1 [patent_app_number] => 7/535774 [patent_app_country] => US [patent_app_date] => 1990-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2603 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/041/05041895.pdf [firstpage_image] =>[orig_patent_app_number] => 535774 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/535774
Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage Jun 7, 1990 Issued
07/535332 INTEGRATED CIRCUIT INDUCTOR Jun 7, 1990 Abandoned
07/528324 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME May 28, 1990 Abandoned
07/529679 CHIP DECOUPLING CAPACITOR May 27, 1990 Abandoned
Array ( [id] => 2877039 [patent_doc_number] => 05153701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-06 [patent_title] => 'Semiconductor device with low defect density oxide' [patent_app_type] => 1 [patent_app_number] => 7/529771 [patent_app_country] => US [patent_app_date] => 1990-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6412 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/153/05153701.pdf [firstpage_image] =>[orig_patent_app_number] => 529771 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/529771
Semiconductor device with low defect density oxide May 24, 1990 Issued
07/521730 A SEMICONDUCTOR POWER DEVICE HAVING WALLLS OF AN INVERTED MESA SHAPE TO IMPROVE POWER HANDLING CAPABILITY May 10, 1990 Abandoned
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