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Tien Quang Dinh

Supervisory Patent Examiner (ID: 8179, Phone: (571)272-6899 , Office: P/3647 )

Most Active Art Unit
3644
Art Unit(s)
3104, 3647, 3641, 3644, 3613
Total Applications
1457
Issued Applications
1028
Pending Applications
118
Abandoned Applications
313

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2301139 [patent_doc_number] => 04697201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-09-29 [patent_title] => 'Power MOS FET with decreased resistance in the conducting state' [patent_app_type] => 1 [patent_app_number] => 6/729094 [patent_app_country] => US [patent_app_date] => 1985-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 20 [patent_no_of_words] => 1728 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/697/04697201.pdf [firstpage_image] =>[orig_patent_app_number] => 729094 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/729094
Power MOS FET with decreased resistance in the conducting state May 1, 1985 Issued
Array ( [id] => 2492597 [patent_doc_number] => 04821085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-11 [patent_title] => 'VLSI local interconnect structure' [patent_app_type] => 1 [patent_app_number] => 6/729318 [patent_app_country] => US [patent_app_date] => 1985-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3622 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/821/04821085.pdf [firstpage_image] =>[orig_patent_app_number] => 729318 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/729318
VLSI local interconnect structure Apr 30, 1985 Issued
06/728431 METHOD AND APPARATUS FOR IMPROVED METAL-INSULATOR-SEMICONDUCTOR DEVICE OPERATION Apr 28, 1985 Abandoned
06/726182 SEMI-CONDCUTOR I.C. ELEMENT Apr 22, 1985 Abandoned
Array ( [id] => 2364454 [patent_doc_number] => 04667217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-05-19 [patent_title] => 'Two bit vertically/horizontally integrated memory cell' [patent_app_type] => 1 [patent_app_number] => 6/725039 [patent_app_country] => US [patent_app_date] => 1985-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5517 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/667/04667217.pdf [firstpage_image] =>[orig_patent_app_number] => 725039 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/725039
Two bit vertically/horizontally integrated memory cell Apr 18, 1985 Issued
06/720862 ELECTROSTATIC DISCHARGE INPUT PROTECTION NETWORK Apr 7, 1985 Abandoned
Array ( [id] => 2306575 [patent_doc_number] => 04673962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-06-16 [patent_title] => 'Vertical DRAM cell and method' [patent_app_type] => 1 [patent_app_number] => 6/714589 [patent_app_country] => US [patent_app_date] => 1985-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4323 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/673/04673962.pdf [firstpage_image] =>[orig_patent_app_number] => 714589 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/714589
Vertical DRAM cell and method Mar 20, 1985 Issued
Array ( [id] => 2631878 [patent_doc_number] => 04920401 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-24 [patent_title] => 'Bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 6/710950 [patent_app_country] => US [patent_app_date] => 1985-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 29 [patent_no_of_words] => 4867 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/920/04920401.pdf [firstpage_image] =>[orig_patent_app_number] => 710950 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/710950
Bipolar transistors Mar 13, 1985 Issued
06/707008 ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY CELL INCLUDING TRENCH CAPACITOR Feb 27, 1985 Abandoned
06/701815 DUAL ELECTRON INJECTOR STRUCTURES USING A CONDUCTIVE OXIDE BETWEEN INJECTORS Feb 18, 1985 Abandoned
Array ( [id] => 2364755 [patent_doc_number] => 04694313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-09-15 [patent_title] => 'Conductivity modulated semiconductor structure' [patent_app_type] => 1 [patent_app_number] => 6/702601 [patent_app_country] => US [patent_app_date] => 1985-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3163 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/694/04694313.pdf [firstpage_image] =>[orig_patent_app_number] => 702601 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/702601
Conductivity modulated semiconductor structure Feb 18, 1985 Issued
06/702609 BREAKDOWN DIODE STRUCTURE Feb 18, 1985 Abandoned
Array ( [id] => 2357654 [patent_doc_number] => 04654690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-31 [patent_title] => 'Capacitive elements with reduced stray capacitance' [patent_app_type] => 1 [patent_app_number] => 6/701218 [patent_app_country] => US [patent_app_date] => 1985-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1135 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/654/04654690.pdf [firstpage_image] =>[orig_patent_app_number] => 701218 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/701218
Capacitive elements with reduced stray capacitance Feb 12, 1985 Issued
Array ( [id] => 2636350 [patent_doc_number] => 04916505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-10 [patent_title] => 'Composite unipolar-bipolar semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 6/699375 [patent_app_country] => US [patent_app_date] => 1985-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 5548 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/916/04916505.pdf [firstpage_image] =>[orig_patent_app_number] => 699375 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/699375
Composite unipolar-bipolar semiconductor devices Feb 6, 1985 Issued
06/698217 PNP TYPE LATERAL TRANSISTOR WITH MINIMAL SUBSTRATE OPERATION INTERFERENCE AND METHOD FOR PRODUCING SAME Feb 3, 1985 Abandoned
Array ( [id] => 2364017 [patent_doc_number] => 04665426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-05-12 [patent_title] => 'EPROM with ultraviolet radiation transparent silicon nitride passivation layer' [patent_app_type] => 1 [patent_app_number] => 6/697364 [patent_app_country] => US [patent_app_date] => 1985-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1763 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/665/04665426.pdf [firstpage_image] =>[orig_patent_app_number] => 697364 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/697364
EPROM with ultraviolet radiation transparent silicon nitride passivation layer Jan 31, 1985 Issued
06/697462 READ ONLY MEMORY AND A METHOD OF MANUFACTURING THE SAME Jan 31, 1985 Abandoned
Array ( [id] => 2479922 [patent_doc_number] => 04887135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-12 [patent_title] => 'Dual level polysilicon single transistor-capacitor memory array' [patent_app_type] => 1 [patent_app_number] => 6/694487 [patent_app_country] => US [patent_app_date] => 1985-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2977 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/887/04887135.pdf [firstpage_image] =>[orig_patent_app_number] => 694487 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/694487
Dual level polysilicon single transistor-capacitor memory array Jan 23, 1985 Issued
06/692853 RADIATION SENSITIVE SEMICONDUCTOR DEVICE Jan 15, 1985 Abandoned
06/690831 SEMICONDUCTOR DEVICE Jan 13, 1985 Abandoned
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