
Tim Miles
Examiner (ID: 17471)
| Most Active Art Unit | 1305 |
| Art Unit(s) | 1101, 2899, 1801, 1724, 1305, 3402 |
| Total Applications | 1774 |
| Issued Applications | 1552 |
| Pending Applications | 28 |
| Abandoned Applications | 194 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 418224
[patent_doc_number] => 07281144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-09
[patent_title] => 'Power management in communication devices'
[patent_app_type] => utility
[patent_app_number] => 10/778535
[patent_app_country] => US
[patent_app_date] => 2004-02-17
[patent_effective_date] => 0000-00-00
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[patent_figures_cnt] => 4
[patent_no_of_words] => 2734
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/281/07281144.pdf
[firstpage_image] =>[orig_patent_app_number] => 10778535
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/778535 | Power management in communication devices | Feb 16, 2004 | Issued |
Array
(
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[patent_doc_number] => 20040172570
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-02
[patent_title] => 'Generator of word clock synchronized with timing reference bit sequence inherent in serial digital signal'
[patent_app_type] => new
[patent_app_number] => 10/778549
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/778549 | Generator of word clock synchronized with timing reference bit sequence inherent in serial digital signal | Feb 16, 2004 | Abandoned |
Array
(
[id] => 481537
[patent_doc_number] => 07228448
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-05
[patent_title] => 'Method for making power supplies smaller and more efficient for high-power PCs'
[patent_app_type] => utility
[patent_app_number] => 10/779279
[patent_app_country] => US
[patent_app_date] => 2004-02-13
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[patent_drawing_sheets_cnt] => 4
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/779279 | Method for making power supplies smaller and more efficient for high-power PCs | Feb 12, 2004 | Issued |
Array
(
[id] => 7247010
[patent_doc_number] => 20040158752
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Power management system and method for electronic circuits'
[patent_app_type] => new
[patent_app_number] => 10/770450
[patent_app_country] => US
[patent_app_date] => 2004-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/770450 | Power management system and method for electronic circuits | Feb 3, 2004 | Abandoned |
Array
(
[id] => 7423865
[patent_doc_number] => 20040183582
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-23
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => new
[patent_app_number] => 10/768441
[patent_app_country] => US
[patent_app_date] => 2004-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[firstpage_image] =>[orig_patent_app_number] => 10768441
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/768441 | Semiconductor integrated circuit | Feb 1, 2004 | Issued |
Array
(
[id] => 400634
[patent_doc_number] => 07296170
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-11-13
[patent_title] => 'Clock controller with clock source fail-safe logic'
[patent_app_type] => utility
[patent_app_number] => 10/764391
[patent_app_country] => US
[patent_app_date] => 2004-01-23
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[pdf_file] => patents/07/296/07296170.pdf
[firstpage_image] =>[orig_patent_app_number] => 10764391
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/764391 | Clock controller with clock source fail-safe logic | Jan 22, 2004 | Issued |
Array
(
[id] => 453465
[patent_doc_number] => 07251740
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[patent_kind] => B2
[patent_issue_date] => 2007-07-31
[patent_title] => 'Apparatus coupling two circuits having different supply voltage sources'
[patent_app_type] => utility
[patent_app_number] => 10/764406
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[patent_app_date] => 2004-01-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/251/07251740.pdf
[firstpage_image] =>[orig_patent_app_number] => 10764406
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/764406 | Apparatus coupling two circuits having different supply voltage sources | Jan 22, 2004 | Issued |
Array
(
[id] => 414846
[patent_doc_number] => 07284143
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-16
[patent_title] => 'System and method for reducing clock skew'
[patent_app_type] => utility
[patent_app_number] => 10/750607
[patent_app_country] => US
[patent_app_date] => 2003-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 6910
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[pdf_file] => patents/07/284/07284143.pdf
[firstpage_image] =>[orig_patent_app_number] => 10750607
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/750607 | System and method for reducing clock skew | Dec 28, 2003 | Issued |
Array
(
[id] => 6999691
[patent_doc_number] => 20050138345
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Autonomic binding of subsystems to system to prevent theft'
[patent_app_type] => utility
[patent_app_number] => 10/738183
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[firstpage_image] =>[orig_patent_app_number] => 10738183
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/738183 | Autonomic binding of subsystems to system to prevent theft | Dec 16, 2003 | Issued |
Array
(
[id] => 7341593
[patent_doc_number] => 20040133809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-08
[patent_title] => 'Method and system for automatically determining compatible and suitable hardware upgrades for computer hardware'
[patent_app_type] => new
[patent_app_number] => 10/737445
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[patent_app_date] => 2003-12-16
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[pdf_file] => publications/A1/0133/20040133809.pdf
[firstpage_image] =>[orig_patent_app_number] => 10737445
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/737445 | Method and system for automatically determining compatible and suitable hardware upgrades for computer hardware | Dec 15, 2003 | Abandoned |
Array
(
[id] => 7185873
[patent_doc_number] => 20050125703
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Method and system for power management including local bounding of device group power consumption'
[patent_app_type] => utility
[patent_app_number] => 10/727320
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/727320 | Method and system for power management including local bounding of device group power consumption | Dec 2, 2003 | Issued |
Array
(
[id] => 7185864
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[patent_title] => 'Method and system for energy management via energy-aware process scheduling'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/727318 | Method and system for energy management via energy-aware process scheduling | Dec 2, 2003 | Abandoned |
Array
(
[id] => 7107264
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[patent_title] => 'Method and system for allowing a system under test (SUT) to boot a plurality of operating systems without a need for local media'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/715961 | Method and system for allowing a system under test (SUT) to boot a plurality of operating systems without a need for local media | Nov 16, 2003 | Issued |
Array
(
[id] => 6941077
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[patent_title] => 'Method and system for efficiently binding a customer order with a processing system assembly in a manufacturing environment'
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Array
(
[id] => 423713
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[patent_title] => 'Graphical view of shutdown process'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/701379 | Graphical view of shutdown process | Nov 2, 2003 | Issued |
Array
(
[id] => 7167173
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[patent_issue_date] => 2005-04-21
[patent_title] => 'Power management over switching fabrics'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/687512 | Power management over switching fabrics | Oct 14, 2003 | Issued |
Array
(
[id] => 633432
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[patent_title] => 'Data paths with receiver timing fixable to a downstream stage and methods of operation thereof'
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Array
(
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Array
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Array
(
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