
Tim Miles
Examiner (ID: 17471)
| Most Active Art Unit | 1305 |
| Art Unit(s) | 1101, 2899, 1801, 1724, 1305, 3402 |
| Total Applications | 1774 |
| Issued Applications | 1552 |
| Pending Applications | 28 |
| Abandoned Applications | 194 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7279153
[patent_doc_number] => 20040061530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-01
[patent_title] => 'Clock conversion apparatus, clock conversion method, video display apparatus, and memory address setting method'
[patent_app_type] => new
[patent_app_number] => 10/637609
[patent_app_country] => US
[patent_app_date] => 2003-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11585
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0061/20040061530.pdf
[firstpage_image] =>[orig_patent_app_number] => 10637609
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/637609 | Clock conversion apparatus, clock conversion method, video display apparatus, and memory address setting method | Aug 10, 2003 | Abandoned |
Array
(
[id] => 582480
[patent_doc_number] => 07159137
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-02
[patent_title] => 'Synchronized communication between multi-processor clusters of multi-cluster computer systems'
[patent_app_type] => utility
[patent_app_number] => 10/635705
[patent_app_country] => US
[patent_app_date] => 2003-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 28
[patent_no_of_words] => 17976
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/159/07159137.pdf
[firstpage_image] =>[orig_patent_app_number] => 10635705
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/635705 | Synchronized communication between multi-processor clusters of multi-cluster computer systems | Aug 4, 2003 | Issued |
Array
(
[id] => 7030483
[patent_doc_number] => 20050021933
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-27
[patent_title] => 'Method for booting computer system with memory card'
[patent_app_type] => utility
[patent_app_number] => 10/624804
[patent_app_country] => US
[patent_app_date] => 2003-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2339
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0021/20050021933.pdf
[firstpage_image] =>[orig_patent_app_number] => 10624804
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/624804 | Method for booting computer system with memory card | Jul 21, 2003 | Issued |
Array
(
[id] => 7030730
[patent_doc_number] => 20050022035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-27
[patent_title] => 'METHOD FOR PCI EXPRESS POWER MANAGEMENT USING A PCI PM MECHANISM IN A COMPUTER SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 10/604439
[patent_app_country] => US
[patent_app_date] => 2003-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2363
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20050022035.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604439
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604439 | Method for PCI express power management using a PCI PM mechanism in a computer system | Jul 20, 2003 | Issued |
Array
(
[id] => 7030731
[patent_doc_number] => 20050022036
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-27
[patent_title] => 'METHOD FOR PCI EXPRESS POWER MANAGEMENT USING A PCI PM MECHANISM IN A COMPUTER SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 10/604440
[patent_app_country] => US
[patent_app_date] => 2003-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1977
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20050022036.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604440
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604440 | Method for PCI Express power management using a PCI PM mechanism in a computer system | Jul 20, 2003 | Issued |
Array
(
[id] => 7474672
[patent_doc_number] => 20040103334
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-27
[patent_title] => 'Pipeline structure'
[patent_app_type] => new
[patent_app_number] => 10/622835
[patent_app_country] => US
[patent_app_date] => 2003-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3528
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0103/20040103334.pdf
[firstpage_image] =>[orig_patent_app_number] => 10622835
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/622835 | Pipeline structure | Jul 17, 2003 | Issued |
Array
(
[id] => 524981
[patent_doc_number] => 07197655
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-27
[patent_title] => 'Lowered PU power usage method and apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/606581
[patent_app_country] => US
[patent_app_date] => 2003-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2054
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/197/07197655.pdf
[firstpage_image] =>[orig_patent_app_number] => 10606581
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/606581 | Lowered PU power usage method and apparatus | Jun 25, 2003 | Issued |
Array
(
[id] => 7081020
[patent_doc_number] => 20050046400
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Controlling operation of a voltage supply according to the activity of a multi-core integrated circuit component or of multiple IC components'
[patent_app_type] => utility
[patent_app_number] => 10/442595
[patent_app_country] => US
[patent_app_date] => 2003-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4028
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0046/20050046400.pdf
[firstpage_image] =>[orig_patent_app_number] => 10442595
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/442595 | Controlling operation of a voltage supply according to the activity of a multi-core integrated circuit component or of multiple IC components | May 20, 2003 | Abandoned |
Array
(
[id] => 7385252
[patent_doc_number] => 20040221181
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-04
[patent_title] => 'Computer power control device'
[patent_app_type] => new
[patent_app_number] => 10/425838
[patent_app_country] => US
[patent_app_date] => 2003-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1826
[patent_no_of_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0221/20040221181.pdf
[firstpage_image] =>[orig_patent_app_number] => 10425838
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/425838 | Computer power control device | Apr 29, 2003 | Abandoned |
Array
(
[id] => 6703174
[patent_doc_number] => 20030226054
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-04
[patent_title] => 'Clock generation circuit and clock generation method'
[patent_app_type] => new
[patent_app_number] => 10/417513
[patent_app_country] => US
[patent_app_date] => 2003-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 7107
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0226/20030226054.pdf
[firstpage_image] =>[orig_patent_app_number] => 10417513
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/417513 | Clock generation circuit and clock generation method | Apr 16, 2003 | Abandoned |
Array
(
[id] => 582877
[patent_doc_number] => 07162656
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-09
[patent_title] => 'Dynamic protection circuit'
[patent_app_type] => utility
[patent_app_number] => 10/395494
[patent_app_country] => US
[patent_app_date] => 2003-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2816
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/162/07162656.pdf
[firstpage_image] =>[orig_patent_app_number] => 10395494
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/395494 | Dynamic protection circuit | Mar 23, 2003 | Issued |
Array
(
[id] => 504086
[patent_doc_number] => 07213160
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-01
[patent_title] => 'Power management apparatus, power management method, and power management system'
[patent_app_type] => utility
[patent_app_number] => 10/386518
[patent_app_country] => US
[patent_app_date] => 2003-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4384
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/213/07213160.pdf
[firstpage_image] =>[orig_patent_app_number] => 10386518
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/386518 | Power management apparatus, power management method, and power management system | Mar 12, 2003 | Issued |
Array
(
[id] => 431442
[patent_doc_number] => 07269752
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-11
[patent_title] => 'Dynamically controlling power consumption within a network node'
[patent_app_type] => utility
[patent_app_number] => 10/384272
[patent_app_country] => US
[patent_app_date] => 2003-03-07
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[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/07/269/07269752.pdf
[firstpage_image] =>[orig_patent_app_number] => 10384272
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/384272 | Dynamically controlling power consumption within a network node | Mar 6, 2003 | Issued |
Array
(
[id] => 610838
[patent_doc_number] => 07152175
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-19
[patent_title] => 'Power supply system'
[patent_app_type] => utility
[patent_app_number] => 10/383455
[patent_app_country] => US
[patent_app_date] => 2003-03-06
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[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 6567
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/152/07152175.pdf
[firstpage_image] =>[orig_patent_app_number] => 10383455
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/383455 | Power supply system | Mar 5, 2003 | Issued |
Array
(
[id] => 7440525
[patent_doc_number] => 20040162974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-19
[patent_title] => 'Method and apparatus for offloaded enhanced boot process'
[patent_app_type] => new
[patent_app_number] => 10/369362
[patent_app_country] => US
[patent_app_date] => 2003-02-18
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0162/20040162974.pdf
[firstpage_image] =>[orig_patent_app_number] => 10369362
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/369362 | Method and apparatus for offloaded enhanced boot process | Feb 17, 2003 | Issued |
Array
(
[id] => 7212037
[patent_doc_number] => 20040071159
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-15
[patent_title] => 'Providing different clock frequencies for different interfaces of a device'
[patent_app_type] => new
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[patent_app_country] => US
[patent_app_date] => 2002-10-14
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20040071159.pdf
[firstpage_image] =>[orig_patent_app_number] => 10269726
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/269726 | Providing different clock frequencies for different interfaces of a device | Oct 13, 2002 | Issued |
Array
(
[id] => 905030
[patent_doc_number] => 07340627
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-03-04
[patent_title] => 'Method and system for supplementing current during enumeration of a USB device'
[patent_app_type] => utility
[patent_app_number] => 10/230184
[patent_app_country] => US
[patent_app_date] => 2002-08-27
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/340/07340627.pdf
[firstpage_image] =>[orig_patent_app_number] => 10230184
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/230184 | Method and system for supplementing current during enumeration of a USB device | Aug 26, 2002 | Issued |