Tim T. Vo

Array ( [id] => 1085004 [patent_doc_number] => 06834317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Network topology for food service equipment items' [patent_app_type] => B2 [patent_app_number] => 09/771432 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2354 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834317.pdf [firstpage_image] =>[orig_patent_app_number] => 09771432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7367285 [patent_doc_number] => 20040015617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Flexible network interfaces and flexible data clocking' [patent_app_type] => new [patent_app_number] => 09/770345 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015617.pdf [firstpage_image] =>[orig_patent_app_number] => 09770345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6888611 [patent_doc_number] => 20010024066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Handheld device, smart card interface device (IFD) and data transmission method' [patent_app_type] => new [patent_app_number] => 09/761053 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4837 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20010024066.pdf [firstpage_image] =>[orig_patent_app_number] => 09761053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1185759 [patent_doc_number] => 06745273 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Automatic deadlock prevention via arbitration switching' [patent_app_type] => B1 [patent_app_number] => 09/759921 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745273.pdf [firstpage_image] =>[orig_patent_app_number] => 09759921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6880994 [patent_doc_number] => 20010032282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Bus protocol independent method and structure for managing transaction priority, ordering and deadlocks in a multi-processing system' [patent_app_type] => new [patent_app_number] => 09/758855 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032282.pdf [firstpage_image] =>[orig_patent_app_number] => 09758855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1185752 [patent_doc_number] => 06745269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Method and apparatus for preservation of data structures for hardware components discovery and initialization' [patent_app_type] => B2 [patent_app_number] => 09/758736 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745269.pdf [firstpage_image] =>[orig_patent_app_number] => 09758736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6889873 [patent_doc_number] => 20010025328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Multiple memory coherence groups in a single system and method therefor' [patent_app_type] => new [patent_app_number] => 09/758856 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5407 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20010025328.pdf [firstpage_image] =>[orig_patent_app_number] => 09758856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6648130 [patent_doc_number] => 20020087774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Method and apparatus for avoiding race condition with edge-triggered interrupts' [patent_app_type] => new [patent_app_number] => 09/752042 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1810 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087774.pdf [firstpage_image] =>[orig_patent_app_number] => 09752042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6839932 [patent_doc_number] => 20030037272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Bus system and method for achieving a stable bus redundancy' [patent_app_type] => new [patent_app_number] => 09/735515 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1857 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20030037272.pdf [firstpage_image] =>[orig_patent_app_number] => 09735515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1240825 [patent_doc_number] => 06691194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Selective association of lock override procedures with queued multimodal lock' [patent_app_type] => B1 [patent_app_number] => 09/724044 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11357 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691194.pdf [firstpage_image] =>[orig_patent_app_number] => 09724044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1178913 [patent_doc_number] => 06757777 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Bus master switching unit' [patent_app_type] => B1 [patent_app_number] => 09/647704 [patent_app_country] => US [patent_app_date] => 2000-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4069 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757777.pdf [firstpage_image] =>[orig_patent_app_number] => 09647704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1020875 [patent_doc_number] => 06892262 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-10 [patent_title] => 'Serial bus interface device' [patent_app_type] => utility [patent_app_number] => 09/714304 [patent_app_country] => US [patent_app_date] => 2000-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/892/06892262.pdf [firstpage_image] =>[orig_patent_app_number] => 09714304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1229030 [patent_doc_number] => 06701401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Method for testing a USB port and the device for the same' [patent_app_type] => B1 [patent_app_number] => 09/706840 [patent_app_country] => US [patent_app_date] => 2000-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1633 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/701/06701401.pdf [firstpage_image] =>[orig_patent_app_number] => 09706840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1243087 [patent_doc_number] => 06684286 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'High-speed block transfer circuit' [patent_app_type] => B1 [patent_app_number] => 09/704719 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6558 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684286.pdf [firstpage_image] =>[orig_patent_app_number] => 09704719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1240823 [patent_doc_number] => 06691193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses' [patent_app_type] => B1 [patent_app_number] => 09/691391 [patent_app_country] => US [patent_app_date] => 2000-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3456 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691193.pdf [firstpage_image] =>[orig_patent_app_number] => 09691391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7630014 [patent_doc_number] => 06636925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Bus interface circuit preparation apparatus and recording medium' [patent_app_type] => B1 [patent_app_number] => 09/686928 [patent_app_country] => US [patent_app_date] => 2000-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 11366 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636925.pdf [firstpage_image] =>[orig_patent_app_number] => 09686928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7633107 [patent_doc_number] => 06658513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Managing locks affected by planned or unplanned reconfiguration of locking facilities' [patent_app_type] => B1 [patent_app_number] => 09/685623 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 14 [patent_no_of_words] => 7107 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658513.pdf [firstpage_image] =>[orig_patent_app_number] => 09685623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1288904 [patent_doc_number] => 06647450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Multiprocessor computer systems with command FIFO buffer at each target device' [patent_app_type] => B1 [patent_app_number] => 09/680652 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2547 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647450.pdf [firstpage_image] =>[orig_patent_app_number] => 09680652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 695175 [patent_doc_number] => 07076586 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-11 [patent_title] => 'Default bus grant to a bus agent' [patent_app_type] => utility [patent_app_number] => 09/680757 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9011 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/076/07076586.pdf [firstpage_image] =>[orig_patent_app_number] => 09680757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1296985 [patent_doc_number] => 06633938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Independent reset of arbiters and agents to allow for delayed agent reset' [patent_app_type] => B1 [patent_app_number] => 09/680525 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6909 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633938.pdf [firstpage_image] =>[orig_patent_app_number] => 09680525 [rel_patent_id] =>[rel_patent_doc_number] =>)