
Tim T. Vo
Supervisory Patent Examiner (ID: 5755, Phone: (571)272-3642 , Office: P/2185 )
| Most Active Art Unit | 2112 |
| Art Unit(s) | 2189, 2168, 2112, 2185, 2111, 2138, 2781, 2181 |
| Total Applications | 545 |
| Issued Applications | 450 |
| Pending Applications | 48 |
| Abandoned Applications | 49 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1513210
[patent_doc_number] => 06442639
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'Docking station for environmental monitoring instruments'
[patent_app_type] => B1
[patent_app_number] => 09/552034
[patent_app_country] => US
[patent_app_date] => 2000-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7469
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/442/06442639.pdf
[firstpage_image] =>[orig_patent_app_number] => 09552034
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/552034 | Docking station for environmental monitoring instruments | Apr 18, 2000 | Issued |
Array
(
[id] => 7630026
[patent_doc_number] => 06636913
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-21
[patent_title] => 'Data length control of access to a data bus'
[patent_app_type] => B1
[patent_app_number] => 09/551861
[patent_app_country] => US
[patent_app_date] => 2000-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5946
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 18
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/636/06636913.pdf
[firstpage_image] =>[orig_patent_app_number] => 09551861
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/551861 | Data length control of access to a data bus | Apr 17, 2000 | Issued |
Array
(
[id] => 1058938
[patent_doc_number] => 06857034
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-02-15
[patent_title] => 'Computer peripheral device incorporating infrared transmissions'
[patent_app_type] => utility
[patent_app_number] => 09/549651
[patent_app_country] => US
[patent_app_date] => 2000-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1201
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/857/06857034.pdf
[firstpage_image] =>[orig_patent_app_number] => 09549651
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/549651 | Computer peripheral device incorporating infrared transmissions | Apr 13, 2000 | Issued |
Array
(
[id] => 1418544
[patent_doc_number] => 06546447
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-08
[patent_title] => 'Method and apparatus for dynamic PCI combining for PCI bridges'
[patent_app_type] => B1
[patent_app_number] => 09/538212
[patent_app_country] => US
[patent_app_date] => 2000-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2425
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/546/06546447.pdf
[firstpage_image] =>[orig_patent_app_number] => 09538212
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/538212 | Method and apparatus for dynamic PCI combining for PCI bridges | Mar 29, 2000 | Issued |
Array
(
[id] => 1521640
[patent_doc_number] => 06502146
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-31
[patent_title] => 'Apparatus and method for dedicated interconnection over a shared external bus'
[patent_app_type] => B1
[patent_app_number] => 09/537087
[patent_app_country] => US
[patent_app_date] => 2000-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4281
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/502/06502146.pdf
[firstpage_image] =>[orig_patent_app_number] => 09537087
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/537087 | Apparatus and method for dedicated interconnection over a shared external bus | Mar 28, 2000 | Issued |
Array
(
[id] => 1240826
[patent_doc_number] => 06691195
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-10
[patent_title] => 'Compact diagnostic connector for a motherboard of data processing system'
[patent_app_type] => B1
[patent_app_number] => 09/519340
[patent_app_country] => US
[patent_app_date] => 2000-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3501
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/691/06691195.pdf
[firstpage_image] =>[orig_patent_app_number] => 09519340
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/519340 | Compact diagnostic connector for a motherboard of data processing system | Mar 5, 2000 | Issued |
Array
(
[id] => 1539341
[patent_doc_number] => 06412075
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Portable computer with low power CD-player mode'
[patent_app_type] => B1
[patent_app_number] => 09/516060
[patent_app_country] => US
[patent_app_date] => 2000-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3673
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/412/06412075.pdf
[firstpage_image] =>[orig_patent_app_number] => 09516060
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/516060 | Portable computer with low power CD-player mode | Feb 29, 2000 | Issued |
Array
(
[id] => 1229025
[patent_doc_number] => 06701399
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-02
[patent_title] => 'Priority mechanism for scheduling isochronous and asynchronous transactions on a shared bus'
[patent_app_type] => B1
[patent_app_number] => 09/514980
[patent_app_country] => US
[patent_app_date] => 2000-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3826
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/701/06701399.pdf
[firstpage_image] =>[orig_patent_app_number] => 09514980
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/514980 | Priority mechanism for scheduling isochronous and asynchronous transactions on a shared bus | Feb 28, 2000 | Issued |
Array
(
[id] => 1508977
[patent_doc_number] => 06467010
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-15
[patent_title] => 'Method and arrangement for passing data between a reference chip and an external bus'
[patent_app_type] => B1
[patent_app_number] => 09/513009
[patent_app_country] => US
[patent_app_date] => 2000-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 5361
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/467/06467010.pdf
[firstpage_image] =>[orig_patent_app_number] => 09513009
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/513009 | Method and arrangement for passing data between a reference chip and an external bus | Feb 24, 2000 | Issued |
Array
(
[id] => 1109692
[patent_doc_number] => 06813669
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-02
[patent_title] => 'Agent provided by USB device for executing USB device dependent program in USB host'
[patent_app_type] => B1
[patent_app_number] => 09/512200
[patent_app_country] => US
[patent_app_date] => 2000-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2198
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/813/06813669.pdf
[firstpage_image] =>[orig_patent_app_number] => 09512200
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/512200 | Agent provided by USB device for executing USB device dependent program in USB host | Feb 23, 2000 | Issued |
Array
(
[id] => 1429067
[patent_doc_number] => 06529978
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-04
[patent_title] => 'Computer input/output (I/O) interface with dynamic I/O adaptor processor bindings'
[patent_app_type] => B1
[patent_app_number] => 09/511506
[patent_app_country] => US
[patent_app_date] => 2000-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 6414
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/529/06529978.pdf
[firstpage_image] =>[orig_patent_app_number] => 09511506
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/511506 | Computer input/output (I/O) interface with dynamic I/O adaptor processor bindings | Feb 22, 2000 | Issued |
Array
(
[id] => 950034
[patent_doc_number] => 06963944
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-11-08
[patent_title] => 'Method and device for the serial transmission of data'
[patent_app_type] => utility
[patent_app_number] => 09/505895
[patent_app_country] => US
[patent_app_date] => 2000-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 6660
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/963/06963944.pdf
[firstpage_image] =>[orig_patent_app_number] => 09505895
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/505895 | Method and device for the serial transmission of data | Feb 16, 2000 | Issued |
Array
(
[id] => 1221667
[patent_doc_number] => 06708236
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-16
[patent_title] => 'Bus control apparatus'
[patent_app_type] => B1
[patent_app_number] => 09/492518
[patent_app_country] => US
[patent_app_date] => 2000-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 108
[patent_figures_cnt] => 116
[patent_no_of_words] => 40603
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/708/06708236.pdf
[firstpage_image] =>[orig_patent_app_number] => 09492518
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/492518 | Bus control apparatus | Jan 26, 2000 | Issued |
Array
(
[id] => 7633105
[patent_doc_number] => 06658515
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-02
[patent_title] => 'Background execution of universal serial bus transactions'
[patent_app_type] => B1
[patent_app_number] => 09/491177
[patent_app_country] => US
[patent_app_date] => 2000-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4565
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/658/06658515.pdf
[firstpage_image] =>[orig_patent_app_number] => 09491177
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/491177 | Background execution of universal serial bus transactions | Jan 24, 2000 | Issued |
Array
(
[id] => 1279316
[patent_doc_number] => 06654832
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-25
[patent_title] => 'Method of initializing a processor and computer system'
[patent_app_type] => B1
[patent_app_number] => 09/493441
[patent_app_country] => US
[patent_app_date] => 2000-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3099
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/654/06654832.pdf
[firstpage_image] =>[orig_patent_app_number] => 09493441
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/493441 | Method of initializing a processor and computer system | Jan 17, 2000 | Issued |
Array
(
[id] => 1573739
[patent_doc_number] => 06499080
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-24
[patent_title] => 'Post write buffer for a dual clock system'
[patent_app_type] => B1
[patent_app_number] => 09/478846
[patent_app_country] => US
[patent_app_date] => 2000-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5078
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/499/06499080.pdf
[firstpage_image] =>[orig_patent_app_number] => 09478846
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/478846 | Post write buffer for a dual clock system | Jan 6, 2000 | Issued |
Array
(
[id] => 645472
[patent_doc_number] => 07124221
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-17
[patent_title] => 'Low latency multi-level communication interface'
[patent_app_type] => utility
[patent_app_number] => 09/478916
[patent_app_country] => US
[patent_app_date] => 2000-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 65
[patent_figures_cnt] => 85
[patent_no_of_words] => 34391
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/124/07124221.pdf
[firstpage_image] =>[orig_patent_app_number] => 09478916
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/478916 | Low latency multi-level communication interface | Jan 5, 2000 | Issued |
Array
(
[id] => 1365097
[patent_doc_number] => 06581127
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-17
[patent_title] => 'Framework and method for inter-element channel transmission'
[patent_app_type] => B1
[patent_app_number] => 09/477286
[patent_app_country] => US
[patent_app_date] => 2000-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3528
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/581/06581127.pdf
[firstpage_image] =>[orig_patent_app_number] => 09477286
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/477286 | Framework and method for inter-element channel transmission | Jan 3, 2000 | Issued |
Array
(
[id] => 945749
[patent_doc_number] => 06968412
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-11-22
[patent_title] => 'Method and apparatus for interrupt controller data re-direction'
[patent_app_type] => utility
[patent_app_number] => 09/476443
[patent_app_country] => US
[patent_app_date] => 1999-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2392
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/968/06968412.pdf
[firstpage_image] =>[orig_patent_app_number] => 09476443
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/476443 | Method and apparatus for interrupt controller data re-direction | Dec 29, 1999 | Issued |
Array
(
[id] => 1279351
[patent_doc_number] => 06654837
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-25
[patent_title] => 'Dynamic priority external transaction system'
[patent_app_type] => B1
[patent_app_number] => 09/474011
[patent_app_country] => US
[patent_app_date] => 1999-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3597
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/654/06654837.pdf
[firstpage_image] =>[orig_patent_app_number] => 09474011
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/474011 | Dynamic priority external transaction system | Dec 27, 1999 | Issued |