Search

Tim T. Vo

Supervisory Patent Examiner (ID: 5755, Phone: (571)272-3642 , Office: P/2185 )

Most Active Art Unit
2112
Art Unit(s)
2189, 2168, 2112, 2185, 2111, 2138, 2781, 2181
Total Applications
545
Issued Applications
450
Pending Applications
48
Abandoned Applications
49

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4203896 [patent_doc_number] => 06151653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'USB/UART converter and its control method' [patent_app_type] => 1 [patent_app_number] => 9/175150 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3351 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151653.pdf [firstpage_image] =>[orig_patent_app_number] => 175150 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175150
USB/UART converter and its control method Oct 18, 1998 Issued
Array ( [id] => 1549511 [patent_doc_number] => 06374318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Filter-circuit for computer system bus' [patent_app_type] => B1 [patent_app_number] => 09/174275 [patent_app_country] => US [patent_app_date] => 1998-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6053 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374318.pdf [firstpage_image] =>[orig_patent_app_number] => 09174275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174275
Filter-circuit for computer system bus Oct 15, 1998 Issued
Array ( [id] => 1567655 [patent_doc_number] => 06438712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Quick identification of defect-uncovering files' [patent_app_type] => B1 [patent_app_number] => 09/169210 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5412 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438712.pdf [firstpage_image] =>[orig_patent_app_number] => 09169210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169210
Quick identification of defect-uncovering files Oct 8, 1998 Issued
Array ( [id] => 1225857 [patent_doc_number] => 06704875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method of operation controller having processor for controlling industrial machine' [patent_app_type] => B1 [patent_app_number] => 09/155827 [patent_app_country] => US [patent_app_date] => 1998-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3976 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704875.pdf [firstpage_image] =>[orig_patent_app_number] => 09155827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/155827
Method of operation controller having processor for controlling industrial machine Oct 5, 1998 Issued
Array ( [id] => 4312722 [patent_doc_number] => 06237103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Power sequencing in a data processing system' [patent_app_type] => 1 [patent_app_number] => 9/163512 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2088 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237103.pdf [firstpage_image] =>[orig_patent_app_number] => 163512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163512
Power sequencing in a data processing system Sep 29, 1998 Issued
Array ( [id] => 1604467 [patent_doc_number] => 06434653 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method and apparatus for disabling power-on in a system requiring add-in modules' [patent_app_type] => B1 [patent_app_number] => 09/163291 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5098 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434653.pdf [firstpage_image] =>[orig_patent_app_number] => 09163291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163291
Method and apparatus for disabling power-on in a system requiring add-in modules Sep 28, 1998 Issued
09/163271 UPGRADE CARD FOR A COMPUTER SYSTEM Sep 28, 1998 Abandoned
Array ( [id] => 4111103 [patent_doc_number] => 06134701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Computer motherboard with a control chip having specific pin arrangement for fast cache access' [patent_app_type] => 1 [patent_app_number] => 9/159441 [patent_app_country] => US [patent_app_date] => 1998-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3034 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 520 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134701.pdf [firstpage_image] =>[orig_patent_app_number] => 159441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159441
Computer motherboard with a control chip having specific pin arrangement for fast cache access Sep 21, 1998 Issued
Array ( [id] => 1466488 [patent_doc_number] => 06393589 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Watchdog timer control circuit with permanent and programmable enablement' [patent_app_type] => B1 [patent_app_number] => 09/154015 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 975 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393589.pdf [firstpage_image] =>[orig_patent_app_number] => 09154015 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154015
Watchdog timer control circuit with permanent and programmable enablement Sep 15, 1998 Issued
Array ( [id] => 1556734 [patent_doc_number] => 06349238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'System and method for managing the workflow for processing service orders among a variety of organizations within a telecommunications company' [patent_app_type] => B1 [patent_app_number] => 09/154233 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15786 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349238.pdf [firstpage_image] =>[orig_patent_app_number] => 09154233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154233
System and method for managing the workflow for processing service orders among a variety of organizations within a telecommunications company Sep 15, 1998 Issued
Array ( [id] => 1481285 [patent_doc_number] => 06389557 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Freezing mechanism for debugging' [patent_app_type] => B1 [patent_app_number] => 09/154077 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 3 [patent_no_of_words] => 3060 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389557.pdf [firstpage_image] =>[orig_patent_app_number] => 09154077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154077
Freezing mechanism for debugging Sep 15, 1998 Issued
Array ( [id] => 4390565 [patent_doc_number] => 06289355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Fast log apply' [patent_app_type] => 1 [patent_app_number] => 9/153998 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2716 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289355.pdf [firstpage_image] =>[orig_patent_app_number] => 153998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153998
Fast log apply Sep 15, 1998 Issued
Array ( [id] => 5803592 [patent_doc_number] => 20020010879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'APPARATUS AND METHOD FOR FAST CODE COVERAGE ANALYSIS' [patent_app_type] => new [patent_app_number] => 09/153389 [patent_app_country] => US [patent_app_date] => 1998-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5241 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010879.pdf [firstpage_image] =>[orig_patent_app_number] => 09153389 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153389
Apparatus and method for fast code coverage analysis Sep 14, 1998 Issued
Array ( [id] => 4424712 [patent_doc_number] => 06266784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Direct storage of recovery plan file on remote server for disaster recovery and storage management thereof' [patent_app_type] => 1 [patent_app_number] => 9/153595 [patent_app_country] => US [patent_app_date] => 1998-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5011 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266784.pdf [firstpage_image] =>[orig_patent_app_number] => 153595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153595
Direct storage of recovery plan file on remote server for disaster recovery and storage management thereof Sep 14, 1998 Issued
Array ( [id] => 4268672 [patent_doc_number] => 06138181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'CPU mode switching circuit changing operation mode responsive to a power on reset signal and an external reset signal' [patent_app_type] => 1 [patent_app_number] => 9/150740 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2456 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138181.pdf [firstpage_image] =>[orig_patent_app_number] => 150740 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150740
CPU mode switching circuit changing operation mode responsive to a power on reset signal and an external reset signal Sep 9, 1998 Issued
Array ( [id] => 4177366 [patent_doc_number] => 06158031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Automated code generating translator for testing telecommunication system devices and method' [patent_app_type] => 1 [patent_app_number] => 9/149369 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/158/06158031.pdf [firstpage_image] =>[orig_patent_app_number] => 149369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149369
Automated code generating translator for testing telecommunication system devices and method Sep 7, 1998 Issued
Array ( [id] => 1501589 [patent_doc_number] => 06405299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity' [patent_app_type] => B1 [patent_app_number] => 09/145139 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 58 [patent_no_of_words] => 13076 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405299.pdf [firstpage_image] =>[orig_patent_app_number] => 09145139 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145139
Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity Aug 27, 1998 Issued
Array ( [id] => 4376118 [patent_doc_number] => 06219733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Transmission line loop' [patent_app_type] => 1 [patent_app_number] => 9/140372 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2264 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219733.pdf [firstpage_image] =>[orig_patent_app_number] => 140372 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140372
Transmission line loop Aug 25, 1998 Issued
Array ( [id] => 4279594 [patent_doc_number] => 06205506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Bus interface unit having multipurpose transaction buffer' [patent_app_type] => 1 [patent_app_number] => 9/139555 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4804 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205506.pdf [firstpage_image] =>[orig_patent_app_number] => 139555 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/139555
Bus interface unit having multipurpose transaction buffer Aug 24, 1998 Issued
Array ( [id] => 4123776 [patent_doc_number] => 06101568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Bus interface unit having dual purpose transaction buffer' [patent_app_type] => 1 [patent_app_number] => 9/139243 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5130 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101568.pdf [firstpage_image] =>[orig_patent_app_number] => 139243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/139243
Bus interface unit having dual purpose transaction buffer Aug 24, 1998 Issued
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