Search

Tim T. Vo

Supervisory Patent Examiner (ID: 3120, Phone: (571)272-3642 , Office: P/2185 )

Most Active Art Unit
2112
Art Unit(s)
2138, 2185, 2189, 2112, 2111, 2168, 2181, 2781
Total Applications
536
Issued Applications
443
Pending Applications
49
Abandoned Applications
48

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1043140 [patent_doc_number] => 06871249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'PCI-X 2.0 receiver with initial offset for biased idle transmission line' [patent_app_type] => utility [patent_app_number] => 10/152872 [patent_app_country] => US [patent_app_date] => 2002-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2223 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/871/06871249.pdf [firstpage_image] =>[orig_patent_app_number] => 10152872 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152872
PCI-X 2.0 receiver with initial offset for biased idle transmission line May 20, 2002 Issued
Array ( [id] => 940376 [patent_doc_number] => 06973516 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Method and apparatus for a controller capable of supporting multiple protocols' [patent_app_type] => utility [patent_app_number] => 10/152663 [patent_app_country] => US [patent_app_date] => 2002-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4484 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/973/06973516.pdf [firstpage_image] =>[orig_patent_app_number] => 10152663 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152663
Method and apparatus for a controller capable of supporting multiple protocols May 19, 2002 Issued
Array ( [id] => 975398 [patent_doc_number] => 06938113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Apparatus for flushing slave transactions from resetting masters of a data bus' [patent_app_type] => utility [patent_app_number] => 10/152265 [patent_app_country] => US [patent_app_date] => 2002-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2865 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/938/06938113.pdf [firstpage_image] =>[orig_patent_app_number] => 10152265 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152265
Apparatus for flushing slave transactions from resetting masters of a data bus May 19, 2002 Issued
Array ( [id] => 6771273 [patent_doc_number] => 20030217213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Method and apparatus for implementing chip-to-chip interconnect bus initialization' [patent_app_type] => new [patent_app_number] => 10/147615 [patent_app_country] => US [patent_app_date] => 2002-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2525 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20030217213.pdf [firstpage_image] =>[orig_patent_app_number] => 10147615 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/147615
Method and apparatus for implementing chip-to-chip interconnect bus initialization May 15, 2002 Issued
Array ( [id] => 771381 [patent_doc_number] => 07010667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity' [patent_app_type] => utility [patent_app_number] => 10/116986 [patent_app_country] => US [patent_app_date] => 2002-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 58 [patent_no_of_words] => 13177 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010667.pdf [firstpage_image] =>[orig_patent_app_number] => 10116986 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/116986
Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity Apr 4, 2002 Issued
Array ( [id] => 7618495 [patent_doc_number] => 06944695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-13 [patent_title] => 'Method and apparatus for connecting devices to a bus' [patent_app_type] => utility [patent_app_number] => 10/107725 [patent_app_country] => US [patent_app_date] => 2002-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2708 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944695.pdf [firstpage_image] =>[orig_patent_app_number] => 10107725 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/107725
Method and apparatus for connecting devices to a bus Mar 24, 2002 Issued
Array ( [id] => 1100337 [patent_doc_number] => 06823410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Split transaction bus system' [patent_app_type] => B2 [patent_app_number] => 10/103337 [patent_app_country] => US [patent_app_date] => 2002-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 9164 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823410.pdf [firstpage_image] =>[orig_patent_app_number] => 10103337 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/103337
Split transaction bus system Mar 20, 2002 Issued
Array ( [id] => 945748 [patent_doc_number] => 06968411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Interrupt processing apparatus, system, and method' [patent_app_type] => utility [patent_app_number] => 10/100718 [patent_app_country] => US [patent_app_date] => 2002-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4580 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/968/06968411.pdf [firstpage_image] =>[orig_patent_app_number] => 10100718 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/100718
Interrupt processing apparatus, system, and method Mar 18, 2002 Issued
Array ( [id] => 5848294 [patent_doc_number] => 20020133651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'PCI extended function interface and PCI device using the same' [patent_app_type] => new [patent_app_number] => 10/100758 [patent_app_country] => US [patent_app_date] => 2002-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2331 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133651.pdf [firstpage_image] =>[orig_patent_app_number] => 10100758 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/100758
PCI extended function interface and PCI device using the same Mar 18, 2002 Issued
Array ( [id] => 6828683 [patent_doc_number] => 20030179741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'High-speed router with single backplane distributing both power and signaling' [patent_app_type] => new [patent_app_number] => 10/068418 [patent_app_country] => US [patent_app_date] => 2002-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20030179741.pdf [firstpage_image] =>[orig_patent_app_number] => 10068418 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/068418
High-speed router with single backplane distributing both power and signaling Feb 4, 2002 Issued
Array ( [id] => 1099245 [patent_doc_number] => 06822876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'High-speed electrical router backplane with noise-isolated power distribution' [patent_app_type] => B2 [patent_app_number] => 10/068420 [patent_app_country] => US [patent_app_date] => 2002-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 30 [patent_no_of_words] => 13740 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822876.pdf [firstpage_image] =>[orig_patent_app_number] => 10068420 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/068420
High-speed electrical router backplane with noise-isolated power distribution Feb 4, 2002 Issued
Array ( [id] => 6788952 [patent_doc_number] => 20030140191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'System, method, and computer program product for on-line replacement of a host bus adapter' [patent_app_type] => new [patent_app_number] => 10/057404 [patent_app_country] => US [patent_app_date] => 2002-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6421 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20030140191.pdf [firstpage_image] =>[orig_patent_app_number] => 10057404 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/057404
System, method, and computer program product for on-line replacement of a host bus adapter Jan 23, 2002 Issued
Array ( [id] => 6762969 [patent_doc_number] => 20030126331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Method, apparatus, and system for multi-line communication' [patent_app_type] => new [patent_app_number] => 10/038467 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3553 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20030126331.pdf [firstpage_image] =>[orig_patent_app_number] => 10038467 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038467
Method, apparatus, and system for multi-line communication Jan 2, 2002 Issued
Array ( [id] => 626310 [patent_doc_number] => 07139859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Inter-queue ordering mechanism' [patent_app_type] => utility [patent_app_number] => 10/039130 [patent_app_country] => US [patent_app_date] => 2001-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5722 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139859.pdf [firstpage_image] =>[orig_patent_app_number] => 10039130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/039130
Inter-queue ordering mechanism Dec 30, 2001 Issued
Array ( [id] => 6762983 [patent_doc_number] => 20030126345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Method and apparatus for converting an external memory access into a local memory access in a processor core' [patent_app_type] => new [patent_app_number] => 10/040904 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2192 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20030126345.pdf [firstpage_image] =>[orig_patent_app_number] => 10040904 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040904
Method and apparatus for converting an external memory access into a local memory access in a processor core Dec 27, 2001 Issued
Array ( [id] => 1180743 [patent_doc_number] => 06754737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method and apparatus to allow dynamic variation of ordering enforcement between transactions in a strongly ordered computer interconnect' [patent_app_type] => B2 [patent_app_number] => 10/035983 [patent_app_country] => US [patent_app_date] => 2001-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4307 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754737.pdf [firstpage_image] =>[orig_patent_app_number] => 10035983 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/035983
Method and apparatus to allow dynamic variation of ordering enforcement between transactions in a strongly ordered computer interconnect Dec 23, 2001 Issued
Array ( [id] => 1082965 [patent_doc_number] => 06836813 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-28 [patent_title] => 'Switching I/O node for connection in a multiprocessor computer system' [patent_app_type] => B1 [patent_app_number] => 09/998758 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5062 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/836/06836813.pdf [firstpage_image] =>[orig_patent_app_number] => 09998758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998758
Switching I/O node for connection in a multiprocessor computer system Nov 29, 2001 Issued
Array ( [id] => 1161261 [patent_doc_number] => 06775728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Method and system for concurrent handler execution in an SMI and PMI-based dispatch-execution framework' [patent_app_type] => B2 [patent_app_number] => 10/011233 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 10180 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775728.pdf [firstpage_image] =>[orig_patent_app_number] => 10011233 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/011233
Method and system for concurrent handler execution in an SMI and PMI-based dispatch-execution framework Nov 14, 2001 Issued
Array ( [id] => 6766900 [patent_doc_number] => 20030101300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Method and system for locking multiple resources in a distributed environment' [patent_app_type] => new [patent_app_number] => 09/992168 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101300.pdf [firstpage_image] =>[orig_patent_app_number] => 09992168 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992168
Method and system for locking multiple resources in a distributed environment Nov 12, 2001 Issued
Array ( [id] => 5937750 [patent_doc_number] => 20020062387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Interface emulation for storage devices' [patent_app_type] => new [patent_app_number] => 10/002782 [patent_app_country] => US [patent_app_date] => 2001-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4704 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20020062387.pdf [firstpage_image] =>[orig_patent_app_number] => 10002782 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002782
Interface emulation for storage devices Oct 28, 2001 Issued
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