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Tima Michele Mcguthry Banks

Examiner (ID: 5677, Phone: (571)272-2744 , Office: P/1733 )

Most Active Art Unit
1733
Art Unit(s)
1793, 1742, 1733, CAO
Total Applications
1792
Issued Applications
1324
Pending Applications
174
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
08/346352 MICROPROCESSOR ARCHITECTURE UTILIZING AN ASYNCHRONOUS BUS BETWEEN MICROPROCESSOR AND INDUSTRY STANDARD SYNCHRONOUS BUS Nov 28, 1994 Abandoned
Array ( [id] => 3776844 [patent_doc_number] => 05742847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'M&A for dynamically generating and maintaining frame based polling schedules for polling isochronous and asynchronous functions that guaranty latencies and bandwidths to the isochronous functions' [patent_app_type] => 1 [patent_app_number] => 8/331727 [patent_app_country] => US [patent_app_date] => 1994-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 10407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742847.pdf [firstpage_image] =>[orig_patent_app_number] => 331727 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/331727
M&A for dynamically generating and maintaining frame based polling schedules for polling isochronous and asynchronous functions that guaranty latencies and bandwidths to the isochronous functions Oct 30, 1994 Issued
Array ( [id] => 3887185 [patent_doc_number] => 05838906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Distributed hypermedia method for automatically invoking external application providing interaction and display of embedded objects within a hypermedia document' [patent_app_type] => 1 [patent_app_number] => 8/324443 [patent_app_country] => US [patent_app_date] => 1994-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 9222 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838906.pdf [firstpage_image] =>[orig_patent_app_number] => 324443 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/324443
Distributed hypermedia method for automatically invoking external application providing interaction and display of embedded objects within a hypermedia document Oct 16, 1994 Issued
Array ( [id] => 3569351 [patent_doc_number] => 05544319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Fiber optic memory coupling system with converter transmitting and receiving bus data in parallel fashion and diagnostic data in serial fashion' [patent_app_type] => 1 [patent_app_number] => 8/320767 [patent_app_country] => US [patent_app_date] => 1994-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 11876 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544319.pdf [firstpage_image] =>[orig_patent_app_number] => 320767 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/320767
Fiber optic memory coupling system with converter transmitting and receiving bus data in parallel fashion and diagnostic data in serial fashion Oct 10, 1994 Issued
Array ( [id] => 3636687 [patent_doc_number] => 05594927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Apparatus and method for aligning data transferred via DMA using a barrel shifter and a buffer comprising of byte-wide, individually addressabe FIFO circuits' [patent_app_type] => 1 [patent_app_number] => 8/306855 [patent_app_country] => US [patent_app_date] => 1994-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9085 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594927.pdf [firstpage_image] =>[orig_patent_app_number] => 306855 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/306855
Apparatus and method for aligning data transferred via DMA using a barrel shifter and a buffer comprising of byte-wide, individually addressabe FIFO circuits Sep 14, 1994 Issued
08/305510 MULTI-PROCESSOR RESOURCE LOCKING MECHANISM Sep 12, 1994 Abandoned
Array ( [id] => 3637369 [patent_doc_number] => 05603056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Disk drive control computer and method for rewriting control program in flash EEPROM with serial communication using unassigned pins of SCSI or ATA connector' [patent_app_type] => 1 [patent_app_number] => 8/302014 [patent_app_country] => US [patent_app_date] => 1994-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603056.pdf [firstpage_image] =>[orig_patent_app_number] => 302014 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/302014
Disk drive control computer and method for rewriting control program in flash EEPROM with serial communication using unassigned pins of SCSI or ATA connector Sep 8, 1994 Issued
Array ( [id] => 3702266 [patent_doc_number] => 05604916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Controlling device for switching serial communication port and light communication port and its driving method' [patent_app_type] => 1 [patent_app_number] => 8/302251 [patent_app_country] => US [patent_app_date] => 1994-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3299 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604916.pdf [firstpage_image] =>[orig_patent_app_number] => 302251 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/302251
Controlling device for switching serial communication port and light communication port and its driving method Sep 7, 1994 Issued
Array ( [id] => 3678295 [patent_doc_number] => 05669014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width' [patent_app_type] => 1 [patent_app_number] => 8/297487 [patent_app_country] => US [patent_app_date] => 1994-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5379 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/669/05669014.pdf [firstpage_image] =>[orig_patent_app_number] => 297487 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/297487
System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width Aug 28, 1994 Issued
Array ( [id] => 3716089 [patent_doc_number] => 05675740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'System for sending messages in a session using a mixture of protocols and preventing usage of a protocol when the message failing to meet a set of criteria' [patent_app_type] => 1 [patent_app_number] => 8/291312 [patent_app_country] => US [patent_app_date] => 1994-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 7576 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675740.pdf [firstpage_image] =>[orig_patent_app_number] => 291312 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/291312
System for sending messages in a session using a mixture of protocols and preventing usage of a protocol when the message failing to meet a set of criteria Aug 15, 1994 Issued
Array ( [id] => 3641725 [patent_doc_number] => 05687316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Communication apparatus and methods having P-MAC, I-MAC engines and buffer bypass for simultaneously transmitting multimedia and packet data' [patent_app_type] => 1 [patent_app_number] => 8/282376 [patent_app_country] => US [patent_app_date] => 1994-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 38 [patent_no_of_words] => 23372 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687316.pdf [firstpage_image] =>[orig_patent_app_number] => 282376 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/282376
Communication apparatus and methods having P-MAC, I-MAC engines and buffer bypass for simultaneously transmitting multimedia and packet data Jul 28, 1994 Issued
Array ( [id] => 3596645 [patent_doc_number] => 05581787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Processing system and method for allocating address space among adapters using slot ID and address information unique to the adapter\'s group' [patent_app_type] => 1 [patent_app_number] => 8/266863 [patent_app_country] => US [patent_app_date] => 1994-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3797 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581787.pdf [firstpage_image] =>[orig_patent_app_number] => 266863 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/266863
Processing system and method for allocating address space among adapters using slot ID and address information unique to the adapter's group Jul 4, 1994 Issued
08/269982 METHOD AND SYSTEM FOR DYNAMICALLY DISPATCHING COLOR PROFILE DATA IN A COLOR MANAGEMENT SYSTEM Jun 30, 1994 Abandoned
Array ( [id] => 3672339 [patent_doc_number] => 05592626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'System and method for selecting cache server based on transmission and storage factors for efficient delivery of multimedia information in a hierarchical network of servers' [patent_app_type] => 1 [patent_app_number] => 8/246246 [patent_app_country] => US [patent_app_date] => 1994-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6207 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592626.pdf [firstpage_image] =>[orig_patent_app_number] => 246246 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/246246
System and method for selecting cache server based on transmission and storage factors for efficient delivery of multimedia information in a hierarchical network of servers May 18, 1994 Issued
Array ( [id] => 3636401 [patent_doc_number] => 05602995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Method and apparatus for buffering data within stations of a communication network with mapping of packet numbers to buffer\'s physical addresses' [patent_app_type] => 1 [patent_app_number] => 8/242496 [patent_app_country] => US [patent_app_date] => 1994-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 19466 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602995.pdf [firstpage_image] =>[orig_patent_app_number] => 242496 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/242496
Method and apparatus for buffering data within stations of a communication network with mapping of packet numbers to buffer's physical addresses May 12, 1994 Issued
Array ( [id] => 3530171 [patent_doc_number] => 05577211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'System and method using chained structure queues for ordering of message delivery between connected nodes wherein unsuccessful message portion is skipped and retried' [patent_app_type] => 1 [patent_app_number] => 8/241920 [patent_app_country] => US [patent_app_date] => 1994-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5470 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577211.pdf [firstpage_image] =>[orig_patent_app_number] => 241920 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/241920
System and method using chained structure queues for ordering of message delivery between connected nodes wherein unsuccessful message portion is skipped and retried May 10, 1994 Issued
Array ( [id] => 3707611 [patent_doc_number] => 05596720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Redundant message processing system featuring reception server controlling communication between client and server process, and stand-by server retransmitting message with information indicating the message being a retransmitted message' [patent_app_type] => 1 [patent_app_number] => 8/237408 [patent_app_country] => US [patent_app_date] => 1994-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 11614 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596720.pdf [firstpage_image] =>[orig_patent_app_number] => 237408 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/237408
Redundant message processing system featuring reception server controlling communication between client and server process, and stand-by server retransmitting message with information indicating the message being a retransmitted message May 2, 1994 Issued
Array ( [id] => 3553627 [patent_doc_number] => 05481754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Apparatus and method for bios interface to features in multiple adapter cards in one operation using registers with bits distributed across the adapter cards' [patent_app_type] => 1 [patent_app_number] => 8/236239 [patent_app_country] => US [patent_app_date] => 1994-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2398 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481754.pdf [firstpage_image] =>[orig_patent_app_number] => 236239 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/236239
Apparatus and method for bios interface to features in multiple adapter cards in one operation using registers with bits distributed across the adapter cards May 1, 1994 Issued
Array ( [id] => 3553638 [patent_doc_number] => 05481755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Apparatus and method for addressing multiple adapter cards in one operation by distributing bits of registers across the adapter cards' [patent_app_type] => 1 [patent_app_number] => 8/236672 [patent_app_country] => US [patent_app_date] => 1994-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2402 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481755.pdf [firstpage_image] =>[orig_patent_app_number] => 236672 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/236672
Apparatus and method for addressing multiple adapter cards in one operation by distributing bits of registers across the adapter cards May 1, 1994 Issued
Array ( [id] => 3612824 [patent_doc_number] => 05560017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'System with clock frequency controller responsive to interrupt independent of software routine and software loop repeatedly executing instruction to slow down system clock' [patent_app_type] => 1 [patent_app_number] => 8/236878 [patent_app_country] => US [patent_app_date] => 1994-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5922 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/560/05560017.pdf [firstpage_image] =>[orig_patent_app_number] => 236878 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/236878
System with clock frequency controller responsive to interrupt independent of software routine and software loop repeatedly executing instruction to slow down system clock Apr 28, 1994 Issued
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