| Application number | Title of the application | Filing Date | Status |
|---|
| 08/346352 | MICROPROCESSOR ARCHITECTURE UTILIZING AN ASYNCHRONOUS BUS BETWEEN MICROPROCESSOR AND INDUSTRY STANDARD SYNCHRONOUS BUS | Nov 28, 1994 | Abandoned |
Array
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[patent_doc_number] => 05742847
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'M&A for dynamically generating and maintaining frame based polling schedules for polling isochronous and asynchronous functions that guaranty latencies and bandwidths to the isochronous functions'
[patent_app_type] => 1
[patent_app_number] => 8/331727
[patent_app_country] => US
[patent_app_date] => 1994-10-31
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[pdf_file] => patents/05/742/05742847.pdf
[firstpage_image] =>[orig_patent_app_number] => 331727
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/331727 | M&A for dynamically generating and maintaining frame based polling schedules for polling isochronous and asynchronous functions that guaranty latencies and bandwidths to the isochronous functions | Oct 30, 1994 | Issued |
Array
(
[id] => 3887185
[patent_doc_number] => 05838906
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Distributed hypermedia method for automatically invoking external application providing interaction and display of embedded objects within a hypermedia document'
[patent_app_type] => 1
[patent_app_number] => 8/324443
[patent_app_country] => US
[patent_app_date] => 1994-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/05/838/05838906.pdf
[firstpage_image] =>[orig_patent_app_number] => 324443
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/324443 | Distributed hypermedia method for automatically invoking external application providing interaction and display of embedded objects within a hypermedia document | Oct 16, 1994 | Issued |
Array
(
[id] => 3569351
[patent_doc_number] => 05544319
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'Fiber optic memory coupling system with converter transmitting and receiving bus data in parallel fashion and diagnostic data in serial fashion'
[patent_app_type] => 1
[patent_app_number] => 8/320767
[patent_app_country] => US
[patent_app_date] => 1994-10-11
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[firstpage_image] =>[orig_patent_app_number] => 320767
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/320767 | Fiber optic memory coupling system with converter transmitting and receiving bus data in parallel fashion and diagnostic data in serial fashion | Oct 10, 1994 | Issued |
Array
(
[id] => 3636687
[patent_doc_number] => 05594927
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-14
[patent_title] => 'Apparatus and method for aligning data transferred via DMA using a barrel shifter and a buffer comprising of byte-wide, individually addressabe FIFO circuits'
[patent_app_type] => 1
[patent_app_number] => 8/306855
[patent_app_country] => US
[patent_app_date] => 1994-09-15
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/306855 | Apparatus and method for aligning data transferred via DMA using a barrel shifter and a buffer comprising of byte-wide, individually addressabe FIFO circuits | Sep 14, 1994 | Issued |
| 08/305510 | MULTI-PROCESSOR RESOURCE LOCKING MECHANISM | Sep 12, 1994 | Abandoned |
Array
(
[id] => 3637369
[patent_doc_number] => 05603056
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-11
[patent_title] => 'Disk drive control computer and method for rewriting control program in flash EEPROM with serial communication using unassigned pins of SCSI or ATA connector'
[patent_app_type] => 1
[patent_app_number] => 8/302014
[patent_app_country] => US
[patent_app_date] => 1994-09-09
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Array
(
[id] => 3702266
[patent_doc_number] => 05604916
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-18
[patent_title] => 'Controlling device for switching serial communication port and light communication port and its driving method'
[patent_app_type] => 1
[patent_app_number] => 8/302251
[patent_app_country] => US
[patent_app_date] => 1994-09-08
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[firstpage_image] =>[orig_patent_app_number] => 302251
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/302251 | Controlling device for switching serial communication port and light communication port and its driving method | Sep 7, 1994 | Issued |
Array
(
[id] => 3678295
[patent_doc_number] => 05669014
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-16
[patent_title] => 'System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width'
[patent_app_type] => 1
[patent_app_number] => 8/297487
[patent_app_country] => US
[patent_app_date] => 1994-08-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/669/05669014.pdf
[firstpage_image] =>[orig_patent_app_number] => 297487
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/297487 | System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width | Aug 28, 1994 | Issued |
Array
(
[id] => 3716089
[patent_doc_number] => 05675740
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'System for sending messages in a session using a mixture of protocols and preventing usage of a protocol when the message failing to meet a set of criteria'
[patent_app_type] => 1
[patent_app_number] => 8/291312
[patent_app_country] => US
[patent_app_date] => 1994-08-16
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[firstpage_image] =>[orig_patent_app_number] => 291312
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/291312 | System for sending messages in a session using a mixture of protocols and preventing usage of a protocol when the message failing to meet a set of criteria | Aug 15, 1994 | Issued |
Array
(
[id] => 3641725
[patent_doc_number] => 05687316
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Communication apparatus and methods having P-MAC, I-MAC engines and buffer bypass for simultaneously transmitting multimedia and packet data'
[patent_app_type] => 1
[patent_app_number] => 8/282376
[patent_app_country] => US
[patent_app_date] => 1994-07-29
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[firstpage_image] =>[orig_patent_app_number] => 282376
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/282376 | Communication apparatus and methods having P-MAC, I-MAC engines and buffer bypass for simultaneously transmitting multimedia and packet data | Jul 28, 1994 | Issued |
Array
(
[id] => 3596645
[patent_doc_number] => 05581787
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Processing system and method for allocating address space among adapters using slot ID and address information unique to the adapter\'s group'
[patent_app_type] => 1
[patent_app_number] => 8/266863
[patent_app_country] => US
[patent_app_date] => 1994-07-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/581/05581787.pdf
[firstpage_image] =>[orig_patent_app_number] => 266863
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/266863 | Processing system and method for allocating address space among adapters using slot ID and address information unique to the adapter's group | Jul 4, 1994 | Issued |
| 08/269982 | METHOD AND SYSTEM FOR DYNAMICALLY DISPATCHING COLOR PROFILE DATA IN A COLOR MANAGEMENT SYSTEM | Jun 30, 1994 | Abandoned |
Array
(
[id] => 3672339
[patent_doc_number] => 05592626
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'System and method for selecting cache server based on transmission and storage factors for efficient delivery of multimedia information in a hierarchical network of servers'
[patent_app_type] => 1
[patent_app_number] => 8/246246
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/246246 | System and method for selecting cache server based on transmission and storage factors for efficient delivery of multimedia information in a hierarchical network of servers | May 18, 1994 | Issued |
Array
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[patent_doc_number] => 05602995
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/242496 | Method and apparatus for buffering data within stations of a communication network with mapping of packet numbers to buffer's physical addresses | May 12, 1994 | Issued |
Array
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[id] => 3530171
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'System and method using chained structure queues for ordering of message delivery between connected nodes wherein unsuccessful message portion is skipped and retried'
[patent_app_type] => 1
[patent_app_number] => 8/241920
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/241920 | System and method using chained structure queues for ordering of message delivery between connected nodes wherein unsuccessful message portion is skipped and retried | May 10, 1994 | Issued |
Array
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[id] => 3707611
[patent_doc_number] => 05596720
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[patent_kind] => NA
[patent_issue_date] => 1997-01-21
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[patent_app_type] => 1
[patent_app_number] => 8/237408
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/237408 | Redundant message processing system featuring reception server controlling communication between client and server process, and stand-by server retransmitting message with information indicating the message being a retransmitted message | May 2, 1994 | Issued |
Array
(
[id] => 3553627
[patent_doc_number] => 05481754
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-02
[patent_title] => 'Apparatus and method for bios interface to features in multiple adapter cards in one operation using registers with bits distributed across the adapter cards'
[patent_app_type] => 1
[patent_app_number] => 8/236239
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[pdf_file] => patents/05/481/05481754.pdf
[firstpage_image] =>[orig_patent_app_number] => 236239
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/236239 | Apparatus and method for bios interface to features in multiple adapter cards in one operation using registers with bits distributed across the adapter cards | May 1, 1994 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 1996-01-02
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Array
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