| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3702572
[patent_doc_number] => 05664231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'PCMCIA interface card for coupling input devices such as barcode scanning engines to personal digital assistants and palmtop computers'
[patent_app_type] => 1
[patent_app_number] => 8/236630
[patent_app_country] => US
[patent_app_date] => 1994-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 24
[patent_no_of_words] => 19376
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 20
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/664/05664231.pdf
[firstpage_image] =>[orig_patent_app_number] => 236630
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/236630 | PCMCIA interface card for coupling input devices such as barcode scanning engines to personal digital assistants and palmtop computers | Apr 28, 1994 | Issued |
Array
(
[id] => 3527004
[patent_doc_number] => 05513375
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'System for compensating data rate between a storage device and a data compression processor using a buffer memory mapped twice into contiguous address space of a host processing unit'
[patent_app_type] => 1
[patent_app_number] => 8/234713
[patent_app_country] => US
[patent_app_date] => 1994-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2751
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/513/05513375.pdf
[firstpage_image] =>[orig_patent_app_number] => 234713
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/234713 | System for compensating data rate between a storage device and a data compression processor using a buffer memory mapped twice into contiguous address space of a host processing unit | Apr 27, 1994 | Issued |
| 08/223643 | FAIL-SAFE COMMUNICATIONS ABORT MECHANISM FOR PARALLEL PORTS | Apr 5, 1994 | Abandoned |
| 08/220942 | MICROPROCESSOR ARCHITECTURE UTILIZING AN ASYNCHRONOUS BUS BETWEEN MICROPROCESSOR AND INDUSTRY STANDARD SYNCHRONOUS BUS | Mar 30, 1994 | Abandoned |
Array
(
[id] => 3661404
[patent_doc_number] => 05640599
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-17
[patent_title] => 'Interconnect system initiating data transfer over launch bus at source\'s clock speed and transfering data over data path at receiver\'s clock speed'
[patent_app_type] => 1
[patent_app_number] => 8/210733
[patent_app_country] => US
[patent_app_date] => 1994-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 13917
[patent_no_of_claims] => 72
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/640/05640599.pdf
[firstpage_image] =>[orig_patent_app_number] => 210733
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/210733 | Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed | Mar 17, 1994 | Issued |
| 08/206144 | I/O MEMORY CARD AND I/O MEMORY CARD CONTROL METHOD | Mar 6, 1994 | Abandoned |
| 08/204896 | MULTI-PROCESSOR RESOURCE LOCKING MECHANISM | Mar 1, 1994 | Abandoned |
Array
(
[id] => 3433136
[patent_doc_number] => 05390300
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-14
[patent_title] => 'Real time I/O operation in a vector processing computer system by running designated processors in privileged mode and bypass the operating system'
[patent_app_type] => 1
[patent_app_number] => 8/200921
[patent_app_country] => US
[patent_app_date] => 1994-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4857
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/390/05390300.pdf
[firstpage_image] =>[orig_patent_app_number] => 200921
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/200921 | Real time I/O operation in a vector processing computer system by running designated processors in privileged mode and bypass the operating system | Feb 21, 1994 | Issued |
Array
(
[id] => 3606389
[patent_doc_number] => 05522090
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Magnetic tape library system wherein write request to a storage unit to be mounted is redirected to a temporary device, and then transferred to the storage unit at an arbitrary time later when the unit is mounted'
[patent_app_type] => 1
[patent_app_number] => 8/194373
[patent_app_country] => US
[patent_app_date] => 1994-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 7109
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/522/05522090.pdf
[firstpage_image] =>[orig_patent_app_number] => 194373
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/194373 | Magnetic tape library system wherein write request to a storage unit to be mounted is redirected to a temporary device, and then transferred to the storage unit at an arbitrary time later when the unit is mounted | Feb 7, 1994 | Issued |
Array
(
[id] => 3544063
[patent_doc_number] => 05583994
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'System for efficient delivery of multimedia information using hierarchical network of servers selectively caching program for a selected time period'
[patent_app_type] => 1
[patent_app_number] => 8/192654
[patent_app_country] => US
[patent_app_date] => 1994-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4620
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/583/05583994.pdf
[firstpage_image] =>[orig_patent_app_number] => 192654
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/192654 | System for efficient delivery of multimedia information using hierarchical network of servers selectively caching program for a selected time period | Feb 6, 1994 | Issued |
Array
(
[id] => 3438385
[patent_doc_number] => 05416918
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-16
[patent_title] => 'Low skew system for interfacing asics by routing internal clock off-chip to external delay element then feeding back to on-chip drivers'
[patent_app_type] => 1
[patent_app_number] => 8/187264
[patent_app_country] => US
[patent_app_date] => 1994-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3992
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/416/05416918.pdf
[firstpage_image] =>[orig_patent_app_number] => 187264
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/187264 | Low skew system for interfacing asics by routing internal clock off-chip to external delay element then feeding back to on-chip drivers | Jan 26, 1994 | Issued |
| 08/184896 | SYSTEM AND METHOD FOR DYNAMIC ALIGNMENT OF ASSOCIATED PORTIONS OF A CODE WORD | Jan 18, 1994 | Abandoned |
Array
(
[id] => 3531859
[patent_doc_number] => 05530809
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-25
[patent_title] => 'Router for parallel computer including arrangement for redirecting messages'
[patent_app_type] => 1
[patent_app_number] => 8/181711
[patent_app_country] => US
[patent_app_date] => 1994-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 79
[patent_figures_cnt] => 84
[patent_no_of_words] => 131594
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 290
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/530/05530809.pdf
[firstpage_image] =>[orig_patent_app_number] => 181711
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/181711 | Router for parallel computer including arrangement for redirecting messages | Jan 13, 1994 | Issued |
| 08/168463 | SYSTEM AND METHOD FOR CASCADING MULTIPLE PROGRAMMABLE INTERRUPT CONTROLLERS IN A MULT-PROCESSING SYSTEM | Dec 15, 1993 | Abandoned |
Array
(
[id] => 3612991
[patent_doc_number] => 05560027
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'Scalable parallel processing systems wherein each hypernode has plural processing modules interconnected by crossbar and each processing module has SCI circuitry for forming multi-dimensional network with other hypernodes'
[patent_app_type] => 1
[patent_app_number] => 8/167663
[patent_app_country] => US
[patent_app_date] => 1993-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4416
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/560/05560027.pdf
[firstpage_image] =>[orig_patent_app_number] => 167663
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/167663 | Scalable parallel processing systems wherein each hypernode has plural processing modules interconnected by crossbar and each processing module has SCI circuitry for forming multi-dimensional network with other hypernodes | Dec 14, 1993 | Issued |
Array
(
[id] => 3595327
[patent_doc_number] => 05581705
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system'
[patent_app_type] => 1
[patent_app_number] => 8/166443
[patent_app_country] => US
[patent_app_date] => 1993-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 14
[patent_no_of_words] => 7950
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/581/05581705.pdf
[firstpage_image] =>[orig_patent_app_number] => 166443
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/166443 | Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system | Dec 12, 1993 | Issued |
| 08/161690 | DISPOSITION FILTERING OF MESSAGES USING A SINGLE ADDRESS AND PROTOCOL TABLE BRIDGE | Dec 2, 1993 | Abandoned |
Array
(
[id] => 3530600
[patent_doc_number] => 05507032
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-09
[patent_title] => 'Multiprocessor I/O request control system forming device drive queue and processor interrupt queue from rows and cells of I/O request table and interrupt request table'
[patent_app_type] => 1
[patent_app_number] => 8/166799
[patent_app_country] => US
[patent_app_date] => 1993-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 24
[patent_no_of_words] => 7150
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/507/05507032.pdf
[firstpage_image] =>[orig_patent_app_number] => 166799
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/166799 | Multiprocessor I/O request control system forming device drive queue and processor interrupt queue from rows and cells of I/O request table and interrupt request table | Dec 1, 1993 | Issued |
Array
(
[id] => 3538021
[patent_doc_number] => 05504929
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-02
[patent_title] => 'Method and apparatus for encoding byte sequence for self-clocked high speed data transfer from a parallel port'
[patent_app_type] => 1
[patent_app_number] => 8/154489
[patent_app_country] => US
[patent_app_date] => 1993-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 23
[patent_no_of_words] => 12151
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/504/05504929.pdf
[firstpage_image] =>[orig_patent_app_number] => 154489
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/154489 | Method and apparatus for encoding byte sequence for self-clocked high speed data transfer from a parallel port | Nov 16, 1993 | Issued |
Array
(
[id] => 3527217
[patent_doc_number] => 05487163
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-23
[patent_title] => 'Fast synchronization of asynchronous signals with a synchronous system'
[patent_app_type] => 1
[patent_app_number] => 8/148030
[patent_app_country] => US
[patent_app_date] => 1993-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1749
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 377
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/487/05487163.pdf
[firstpage_image] =>[orig_patent_app_number] => 148030
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/148030 | Fast synchronization of asynchronous signals with a synchronous system | Nov 3, 1993 | Issued |