Search

Tima Michele Mcguthry Banks

Examiner (ID: 5677, Phone: (571)272-2744 , Office: P/1733 )

Most Active Art Unit
1733
Art Unit(s)
1793, 1742, 1733, CAO
Total Applications
1792
Issued Applications
1324
Pending Applications
174
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
07/972515 MICROCOMPUTER ARCHITECTURE UTILIZING ASYNCHRONOUS BUS BETWEEN MICROPROCESSOR AND INDUSTRY STANDARD SYNCHRONOUS BUS Nov 5, 1992 Abandoned
Array ( [id] => 3569419 [patent_doc_number] => 05544324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Network for transmitting isochronous-source data using a frame structure with variable number of time slots to compensate for timing variance between reference clock and data rate' [patent_app_type] => 1 [patent_app_number] => 7/969911 [patent_app_country] => US [patent_app_date] => 1992-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7472 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544324.pdf [firstpage_image] =>[orig_patent_app_number] => 969911 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/969911
Network for transmitting isochronous-source data using a frame structure with variable number of time slots to compensate for timing variance between reference clock and data rate Nov 1, 1992 Issued
07/965854 INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS Oct 22, 1992 Abandoned
Array ( [id] => 3089823 [patent_doc_number] => 05297262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Methods and apparatus for dynamically managing input/output (I/O) connectivity' [patent_app_type] => 1 [patent_app_number] => 7/964571 [patent_app_country] => US [patent_app_date] => 1992-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17069 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297262.pdf [firstpage_image] =>[orig_patent_app_number] => 964571 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/964571
Methods and apparatus for dynamically managing input/output (I/O) connectivity Oct 20, 1992 Issued
Array ( [id] => 3548887 [patent_doc_number] => 05495580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Ring network security system with encoding of data entering a subnetwork and decoding of data leaving a subnetwork' [patent_app_type] => 1 [patent_app_number] => 7/963726 [patent_app_country] => US [patent_app_date] => 1992-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4991 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495580.pdf [firstpage_image] =>[orig_patent_app_number] => 963726 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/963726
Ring network security system with encoding of data entering a subnetwork and decoding of data leaving a subnetwork Oct 19, 1992 Issued
Array ( [id] => 3673286 [patent_doc_number] => 05592685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Synchronous/asynchronous partitioning of an asynchronous bus interface' [patent_app_type] => 1 [patent_app_number] => 7/957977 [patent_app_country] => US [patent_app_date] => 1992-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 18317 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592685.pdf [firstpage_image] =>[orig_patent_app_number] => 957977 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/957977
Synchronous/asynchronous partitioning of an asynchronous bus interface Oct 6, 1992 Issued
Array ( [id] => 4144295 [patent_doc_number] => 06106562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Apparatus and methods for predicting physical and chemical properties of materials' [patent_app_type] => 1 [patent_app_number] => 7/935545 [patent_app_country] => US [patent_app_date] => 1992-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/106/06106562.pdf [firstpage_image] =>[orig_patent_app_number] => 935545 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/935545
Apparatus and methods for predicting physical and chemical properties of materials Aug 25, 1992 Issued
07/930587 NETWORK PRIORITY MANAGEMENT Aug 16, 1992 Abandoned
Array ( [id] => 3569280 [patent_doc_number] => 05502837 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Method and apparatus for clocking variable pixel frequencies and pixel depths in a memory display interface' [patent_app_type] => 1 [patent_app_number] => 7/928513 [patent_app_country] => US [patent_app_date] => 1992-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4169 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502837.pdf [firstpage_image] =>[orig_patent_app_number] => 928513 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/928513
Method and apparatus for clocking variable pixel frequencies and pixel depths in a memory display interface Aug 10, 1992 Issued
Array ( [id] => 3506836 [patent_doc_number] => 05537643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Image forming managing apparatus for setting of communication control data from a remote location only when the communication control data has been invalidated' [patent_app_type] => 1 [patent_app_number] => 7/925206 [patent_app_country] => US [patent_app_date] => 1992-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 2475 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537643.pdf [firstpage_image] =>[orig_patent_app_number] => 925206 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/925206
Image forming managing apparatus for setting of communication control data from a remote location only when the communication control data has been invalidated Aug 5, 1992 Issued
Array ( [id] => 3439539 [patent_doc_number] => 05455950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Universal device for coupling a computer bus to a specific link of a network and operating system therefor' [patent_app_type] => 1 [patent_app_number] => 7/913366 [patent_app_country] => US [patent_app_date] => 1992-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7494 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455950.pdf [firstpage_image] =>[orig_patent_app_number] => 913366 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/913366
Universal device for coupling a computer bus to a specific link of a network and operating system therefor Jul 14, 1992 Issued
Array ( [id] => 3636360 [patent_doc_number] => 05594909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'File I/O control device writing blocks to faster device first and canceling exclusive lock as each block is written' [patent_app_type] => 1 [patent_app_number] => 7/910847 [patent_app_country] => US [patent_app_date] => 1992-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3485 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594909.pdf [firstpage_image] =>[orig_patent_app_number] => 910847 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/910847
File I/O control device writing blocks to faster device first and canceling exclusive lock as each block is written Jul 5, 1992 Issued
Array ( [id] => 3424203 [patent_doc_number] => 05412782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-02 [patent_title] => 'Programmed I/O ethernet adapter with early interrupts for accelerating data transfer' [patent_app_type] => 1 [patent_app_number] => 7/907946 [patent_app_country] => US [patent_app_date] => 1992-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5026 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/412/05412782.pdf [firstpage_image] =>[orig_patent_app_number] => 907946 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/907946
Programmed I/O ethernet adapter with early interrupts for accelerating data transfer Jul 1, 1992 Issued
Array ( [id] => 3589589 [patent_doc_number] => 05524268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Flexible processor-driven control of SCSI buses utilizing tags appended to data bytes to determine SCSI-protocol phases' [patent_app_type] => 1 [patent_app_number] => 7/904807 [patent_app_country] => US [patent_app_date] => 1992-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 9182 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/524/05524268.pdf [firstpage_image] =>[orig_patent_app_number] => 904807 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/904807
Flexible processor-driven control of SCSI buses utilizing tags appended to data bytes to determine SCSI-protocol phases Jun 25, 1992 Issued
Array ( [id] => 3454102 [patent_doc_number] => 05430845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Peripheral device interface for dynamically selecting boot disk device driver' [patent_app_type] => 1 [patent_app_number] => 7/900160 [patent_app_country] => US [patent_app_date] => 1992-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 5489 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430845.pdf [firstpage_image] =>[orig_patent_app_number] => 900160 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/900160
Peripheral device interface for dynamically selecting boot disk device driver Jun 16, 1992 Issued
Array ( [id] => 3501002 [patent_doc_number] => 05475860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Input/output control system and method for direct memory transfer according to location addresses provided by the source unit and destination addresses provided by the destination unit' [patent_app_type] => 1 [patent_app_number] => 7/898157 [patent_app_country] => US [patent_app_date] => 1992-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 17455 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475860.pdf [firstpage_image] =>[orig_patent_app_number] => 898157 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/898157
Input/output control system and method for direct memory transfer according to location addresses provided by the source unit and destination addresses provided by the destination unit Jun 14, 1992 Issued
07/893433 SEMICONDUCTOR DISK UNIT Jun 3, 1992 Abandoned
Array ( [id] => 3495223 [patent_doc_number] => 05446867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Microprocessor PLL clock circuit with selectable delayed feedback' [patent_app_type] => 1 [patent_app_number] => 7/890937 [patent_app_country] => US [patent_app_date] => 1992-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2566 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446867.pdf [firstpage_image] =>[orig_patent_app_number] => 890937 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/890937
Microprocessor PLL clock circuit with selectable delayed feedback May 28, 1992 Issued
Array ( [id] => 3807637 [patent_doc_number] => 05727151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Message control system specifying message storage buffer for data communication system with general purpose and arbitrary form buffers' [patent_app_type] => 1 [patent_app_number] => 7/859397 [patent_app_country] => US [patent_app_date] => 1992-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 18795 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/727/05727151.pdf [firstpage_image] =>[orig_patent_app_number] => 859397 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/859397
Message control system specifying message storage buffer for data communication system with general purpose and arbitrary form buffers May 27, 1992 Issued
07/886301 METHOD AND APPARATUS FOR TRANSFERRING DATA THROUGH A STAGING MEMORY May 20, 1992 Abandoned
Menu