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Tima Michele Mcguthry Banks

Examiner (ID: 5677, Phone: (571)272-2744 , Office: P/1733 )

Most Active Art Unit
1733
Art Unit(s)
1793, 1742, 1733, CAO
Total Applications
1792
Issued Applications
1324
Pending Applications
174
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
07/667337 CONTROL SYSTEM FOR MULTI-PROCESSOR SYSTEM Mar 10, 1991 Abandoned
Array ( [id] => 2947671 [patent_doc_number] => 05247617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Method for supplying data to a buffered UART' [patent_app_type] => 1 [patent_app_number] => 7/661987 [patent_app_country] => US [patent_app_date] => 1991-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247617.pdf [firstpage_image] =>[orig_patent_app_number] => 661987 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/661987
Method for supplying data to a buffered UART Feb 25, 1991 Issued
Array ( [id] => 3533108 [patent_doc_number] => 05530888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Process and apparatus for controlling a programmable controller with efficient identification of operation completion' [patent_app_type] => 1 [patent_app_number] => 7/655697 [patent_app_country] => US [patent_app_date] => 1991-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5506 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530888.pdf [firstpage_image] =>[orig_patent_app_number] => 655697 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/655697
Process and apparatus for controlling a programmable controller with efficient identification of operation completion Feb 14, 1991 Issued
07/654406 SYSTEM CLOCK FREQUENCY CONTROLLER Feb 7, 1991 Abandoned
Array ( [id] => 3553306 [patent_doc_number] => 05481734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Data processor having 2n bits width data bus for context switching function' [patent_app_type] => 1 [patent_app_number] => 7/627066 [patent_app_country] => US [patent_app_date] => 1990-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 18663 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481734.pdf [firstpage_image] =>[orig_patent_app_number] => 627066 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/627066
Data processor having 2n bits width data bus for context switching function Dec 12, 1990 Issued
Array ( [id] => 3094716 [patent_doc_number] => 05280584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Two-way data transfer apparatus' [patent_app_type] => 1 [patent_app_number] => 7/614777 [patent_app_country] => US [patent_app_date] => 1990-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3985 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280584.pdf [firstpage_image] =>[orig_patent_app_number] => 614777 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/614777
Two-way data transfer apparatus Nov 4, 1990 Issued
07/593438 FAST SYNCHRONIZATION OF ASYNCHRONOUS SIGNALS WITH A SYNCHRONOUS SYSTEM Oct 4, 1990 Abandoned
07/582077 SYSTEM AND METHOD FOR COMMUNICATION BETWEEN WINDOWING ENVIRONMENTS Sep 13, 1990 Abandoned
Array ( [id] => 3437475 [patent_doc_number] => 05404453 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Terminals coupling system using bridge interfaces, located inside the host controller, with timer to determine start and end of transmission period' [patent_app_type] => 1 [patent_app_number] => 7/581857 [patent_app_country] => US [patent_app_date] => 1990-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3746 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404453.pdf [firstpage_image] =>[orig_patent_app_number] => 581857 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/581857
Terminals coupling system using bridge interfaces, located inside the host controller, with timer to determine start and end of transmission period Sep 12, 1990 Issued
Array ( [id] => 3079618 [patent_doc_number] => 05353433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-04 [patent_title] => 'Method and apparatus for organizing and analyzing timing information' [patent_app_type] => 1 [patent_app_number] => 7/578723 [patent_app_country] => US [patent_app_date] => 1990-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 8817 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/353/05353433.pdf [firstpage_image] =>[orig_patent_app_number] => 578723 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/578723
Method and apparatus for organizing and analyzing timing information Sep 5, 1990 Issued
Array ( [id] => 3023634 [patent_doc_number] => 05276813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Acquiring addresses in an input/output system' [patent_app_type] => 1 [patent_app_number] => 7/576557 [patent_app_country] => US [patent_app_date] => 1990-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5353 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276813.pdf [firstpage_image] =>[orig_patent_app_number] => 576557 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/576557
Acquiring addresses in an input/output system Aug 30, 1990 Issued
Array ( [id] => 3456389 [patent_doc_number] => 05388216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Circuit for controlling generation of an acknowledge signal and a busy signal in a centronics compatible parallel interface' [patent_app_type] => 1 [patent_app_number] => 7/565477 [patent_app_country] => US [patent_app_date] => 1990-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2405 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388216.pdf [firstpage_image] =>[orig_patent_app_number] => 565477 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/565477
Circuit for controlling generation of an acknowledge signal and a busy signal in a centronics compatible parallel interface Aug 9, 1990 Issued
07/558311 CIRCUIT THAT MINIMIZES THE SKEW BETWEEN SYSTEMS CLOCK AND CONTROL SIGNALS Jul 25, 1990 Abandoned
Array ( [id] => 3052933 [patent_doc_number] => 05377322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Information handling method and system utilizing multiple interconnected processors and controllers' [patent_app_type] => 1 [patent_app_number] => 7/553406 [patent_app_country] => US [patent_app_date] => 1990-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 10923 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377322.pdf [firstpage_image] =>[orig_patent_app_number] => 553406 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/553406
Information handling method and system utilizing multiple interconnected processors and controllers Jul 16, 1990 Issued
07/545960 METHOD FOR OBSERVING THE EXECUTION OF A PROGRAM LOADED INTO AN INFORMATION PROCESSING SYSTEM, AND APPARATUS FOR PERFORMING THE METHOD Jul 1, 1990 Abandoned
07/546037 MULTI-PROCESSOR RESOURCE LOCKING MECHANISM Jun 27, 1990 Abandoned
Array ( [id] => 3023551 [patent_doc_number] => 05333267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Ring interconnect system architecture' [patent_app_type] => 1 [patent_app_number] => 7/530096 [patent_app_country] => US [patent_app_date] => 1990-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7810 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 551 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/333/05333267.pdf [firstpage_image] =>[orig_patent_app_number] => 530096 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/530096
Ring interconnect system architecture May 28, 1990 Issued
Array ( [id] => 2988237 [patent_doc_number] => 05226120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Apparatus and method of monitoring the status of a local area network' [patent_app_type] => 1 [patent_app_number] => 7/526567 [patent_app_country] => US [patent_app_date] => 1990-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 15171 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226120.pdf [firstpage_image] =>[orig_patent_app_number] => 526567 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/526567
Apparatus and method of monitoring the status of a local area network May 20, 1990 Issued
Array ( [id] => 3035041 [patent_doc_number] => 05327532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Coordinated sync point management of protected resources' [patent_app_type] => 1 [patent_app_number] => 7/525427 [patent_app_country] => US [patent_app_date] => 1990-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 68 [patent_no_of_words] => 40433 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327532.pdf [firstpage_image] =>[orig_patent_app_number] => 525427 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/525427
Coordinated sync point management of protected resources May 15, 1990 Issued
Array ( [id] => 2901729 [patent_doc_number] => 05239633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-24 [patent_title] => 'Data processor executing memory indirect addressing and register indirect addressing' [patent_app_type] => 1 [patent_app_number] => 7/497375 [patent_app_country] => US [patent_app_date] => 1990-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6094 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/239/05239633.pdf [firstpage_image] =>[orig_patent_app_number] => 497375 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/497375
Data processor executing memory indirect addressing and register indirect addressing May 3, 1990 Issued
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