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Tima Michele Mcguthry Banks

Examiner (ID: 5677, Phone: (571)272-2744 , Office: P/1733 )

Most Active Art Unit
1733
Art Unit(s)
1793, 1742, 1733, CAO
Total Applications
1792
Issued Applications
1324
Pending Applications
174
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
07/505446 DATA FLOW CONTROLLER AND METHOD Apr 5, 1990 Abandoned
07/494824 MULTI-PROCESSOR COMPUTER SYSTEMS HAVING SHARED MEMORY AND PRIVATE CACHE MEMORIES Mar 14, 1990 Abandoned
07/482597 PHASE DELAY COMPENSATOR Feb 20, 1990 Abandoned
Array ( [id] => 2961879 [patent_doc_number] => 05222240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-22 [patent_title] => 'Method and apparatus for delaying writing back the results of instructions to a processor' [patent_app_type] => 1 [patent_app_number] => 7/479627 [patent_app_country] => US [patent_app_date] => 1990-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3846 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/222/05222240.pdf [firstpage_image] =>[orig_patent_app_number] => 479627 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/479627
Method and apparatus for delaying writing back the results of instructions to a processor Feb 13, 1990 Issued
07/454277 SYSTEM FOR CONTROLLING A VARIABLE SOURCE BY THE FEEDBACK OF THE RUNNING MODE AND RELEVANT CIRCUIT Dec 20, 1989 Abandoned
07/436796 INFORMATION PROCESSING SYSTEM AND METHOD FOR DETERMINING THE CONFIGURATION THEREOF Nov 14, 1989 Abandoned
Array ( [id] => 2951550 [patent_doc_number] => 05191657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-02 [patent_title] => 'Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus' [patent_app_type] => 1 [patent_app_number] => 7/433982 [patent_app_country] => US [patent_app_date] => 1989-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11677 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/191/05191657.pdf [firstpage_image] =>[orig_patent_app_number] => 433982 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/433982
Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus Nov 8, 1989 Issued
Array ( [id] => 2946605 [patent_doc_number] => 05220651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-15 [patent_title] => 'CPU-bus controller for accomplishing transfer operations between a controller and devices coupled to an input/output bus' [patent_app_type] => 1 [patent_app_number] => 7/419096 [patent_app_country] => US [patent_app_date] => 1989-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 15 [patent_no_of_words] => 4445 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/220/05220651.pdf [firstpage_image] =>[orig_patent_app_number] => 419096 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/419096
CPU-bus controller for accomplishing transfer operations between a controller and devices coupled to an input/output bus Oct 10, 1989 Issued
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