Search

Timor Karimy

Examiner (ID: 16056, Phone: (571)272-9006 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2815, 2818, 2894
Total Applications
1353
Issued Applications
1056
Pending Applications
122
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18040440 [patent_doc_number] => 20220384657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => TRANSISTOR, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/884276 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884276 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884276
TRANSISTOR, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING TRANSISTOR Aug 8, 2022 Pending
Array ( [id] => 18967569 [patent_doc_number] => 11901351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Three dimensional integrated circuit with lateral connection layer [patent_app_type] => utility [patent_app_number] => 17/883477 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 12979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883477 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883477
Three dimensional integrated circuit with lateral connection layer Aug 7, 2022 Issued
Array ( [id] => 18024266 [patent_doc_number] => 20220375765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LEAD FRAME, CHIP PACKAGE STRUCTURE, AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/879945 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/879945
LEAD FRAME, CHIP PACKAGE STRUCTURE, AND MANUFACTURING METHOD THEREOF Aug 2, 2022 Pending
Array ( [id] => 18936548 [patent_doc_number] => 11889004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => PUF-film and method for producing the same [patent_app_type] => utility [patent_app_number] => 17/816315 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 47 [patent_no_of_words] => 35002 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816315 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/816315
PUF-film and method for producing the same Jul 28, 2022 Issued
Array ( [id] => 18940862 [patent_doc_number] => 20240036001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => Miniature-Target-Detecting Transistors With Different Gate Structures [patent_app_type] => utility [patent_app_number] => 17/876819 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876819
Miniature-Target-Detecting Transistors With Different Gate Structures Jul 28, 2022 Pending
Array ( [id] => 18857399 [patent_doc_number] => 11854994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Redistribution structure for integrated circuit package and method of forming same [patent_app_type] => utility [patent_app_number] => 17/815660 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 75 [patent_no_of_words] => 21777 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815660 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815660
Redistribution structure for integrated circuit package and method of forming same Jul 27, 2022 Issued
Array ( [id] => 19168459 [patent_doc_number] => 11984372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Integrated circuit package and method [patent_app_type] => utility [patent_app_number] => 17/875656 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 50 [patent_no_of_words] => 17426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875656 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875656
Integrated circuit package and method Jul 27, 2022 Issued
Array ( [id] => 17993375 [patent_doc_number] => 20220359412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR DEVICE HAVING AN EXTRA LOW-K DIELECTRIC LAYER AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/874283 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874283 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874283
Semiconductor device having an extra low-k dielectric layer and method of forming the same Jul 25, 2022 Issued
Array ( [id] => 17993762 [patent_doc_number] => 20220359799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => MONOLITHIC LED ARRAY STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/874038 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874038
MONOLITHIC LED ARRAY STRUCTURE Jul 25, 2022 Abandoned
Array ( [id] => 18008647 [patent_doc_number] => 20220367414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/814853 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814853
Semiconductor structure and manufacturing method thereof Jul 25, 2022 Issued
Array ( [id] => 20205631 [patent_doc_number] => 12408428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Integrated circuit, method for forming a layout of integrated circuit using standard cells [patent_app_type] => utility [patent_app_number] => 17/869797 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1233 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869797
Integrated circuit, method for forming a layout of integrated circuit using standard cells Jul 20, 2022 Issued
Array ( [id] => 18113025 [patent_doc_number] => 20230005905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => Facilitating Alignment of Stacked Chiplets [patent_app_type] => utility [patent_app_number] => 17/867833 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/867833
Facilitating alignment of stacked chiplets Jul 18, 2022 Issued
Array ( [id] => 20203345 [patent_doc_number] => 12406125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Integrated circuit layout including standard cells and method to form the same [patent_app_type] => utility [patent_app_number] => 17/868770 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1249 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868770
Integrated circuit layout including standard cells and method to form the same Jul 18, 2022 Issued
Array ( [id] => 17963696 [patent_doc_number] => 20220344277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => FAN-OUT PACKAGING STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/860328 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860328 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860328
FAN-OUT PACKAGING STRUCTURE Jul 7, 2022 Abandoned
Array ( [id] => 17949343 [patent_doc_number] => 20220336362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/857186 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857186
Semiconductor packages and methods of forming the same Jul 4, 2022 Issued
Array ( [id] => 19966848 [patent_doc_number] => 12336388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Thin film transistor, method for fabricating the thin film transistor, thin film transistor array substrate, and method for fabricating the thin film transistor array substrate [patent_app_type] => utility [patent_app_number] => 17/854584 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7885 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854584 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854584
Thin film transistor, method for fabricating the thin film transistor, thin film transistor array substrate, and method for fabricating the thin film transistor array substrate Jun 29, 2022 Issued
Array ( [id] => 18351463 [patent_doc_number] => 20230139574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING A FIELD EFFECT TRANSISTOR AND A METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/851289 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851289
Semiconductor device including a field effect transistor and a method of fabricating the semiconductor device Jun 27, 2022 Issued
Array ( [id] => 17933330 [patent_doc_number] => 20220328456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => SEMICONDUCTOR ASSEMBLIES WITH HYBRID FANOUTS AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/850992 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850992
Semiconductor assemblies with hybrid fanouts and associated methods and systems Jun 26, 2022 Issued
Array ( [id] => 18112945 [patent_doc_number] => 20230005825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING SUBSTRATE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/848493 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848493
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING SUBSTRATE AND SEMICONDUCTOR DEVICE Jun 23, 2022 Pending
Array ( [id] => 19183768 [patent_doc_number] => 11990368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Doped selective metal caps to improve copper electromigration with ruthenium liner [patent_app_type] => utility [patent_app_number] => 17/848162 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4502 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848162 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848162
Doped selective metal caps to improve copper electromigration with ruthenium liner Jun 22, 2022 Issued
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