Search

Timor Karimy

Examiner (ID: 16056, Phone: (571)272-9006 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2815, 2818, 2894
Total Applications
1353
Issued Applications
1056
Pending Applications
122
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17566652 [patent_doc_number] => 20220130801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => SEMICONDUCTOR PACKAGE HAVING STACKED SEMICONDUCTOR CHIPS [patent_app_type] => utility [patent_app_number] => 17/568558 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568558
Semiconductor package having stacked semiconductor chips Jan 3, 2022 Issued
Array ( [id] => 20259100 [patent_doc_number] => 12431465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Chip package and method of forming chip packages [patent_app_type] => utility [patent_app_number] => 17/566661 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 3444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566661 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566661
Chip package and method of forming chip packages Dec 29, 2021 Issued
Array ( [id] => 19597154 [patent_doc_number] => 12155008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Micro-LED structure and micro-LED chip including same [patent_app_type] => utility [patent_app_number] => 17/562272 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 55 [patent_no_of_words] => 18631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562272 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562272
Micro-LED structure and micro-LED chip including same Dec 26, 2021 Issued
Array ( [id] => 19582727 [patent_doc_number] => 12148858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Micro-LED structure and micro-LED chip including same [patent_app_type] => utility [patent_app_number] => 17/562168 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 55 [patent_no_of_words] => 18631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562168
Micro-LED structure and micro-LED chip including same Dec 26, 2021 Issued
Array ( [id] => 18578927 [patent_doc_number] => 11735467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Airgap formation processes [patent_app_type] => utility [patent_app_number] => 17/558848 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7865 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558848
Airgap formation processes Dec 21, 2021 Issued
Array ( [id] => 18456381 [patent_doc_number] => 20230197663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => METHOD OF PROCESSING A SEMICONDUCTOR WAFER, SEMICONDUCTOR DIE, AND METHOD OF PRODUCING A SEMICONDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 17/555709 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555709 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555709
Method of processing a semiconductor wafer, semiconductor die, and method of producing a semiconductor module Dec 19, 2021 Issued
Array ( [id] => 18608233 [patent_doc_number] => 11749712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => High dielectric constant material at locations of high fields [patent_app_type] => utility [patent_app_number] => 17/556258 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4562 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556258 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556258
High dielectric constant material at locations of high fields Dec 19, 2021 Issued
Array ( [id] => 17536823 [patent_doc_number] => 20220115432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => IMAGE SENSOR FOR HIGH PHOTOELECTRIC CONVERSION EFFICIENCY AND LOW DARK CURRENT [patent_app_type] => utility [patent_app_number] => 17/555977 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555977
Image sensor for high photoelectric conversion efficiency and low dark current Dec 19, 2021 Issued
Array ( [id] => 18562988 [patent_doc_number] => 11728241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Power device embedded driver board assemblies with cooling structures and methods thereof [patent_app_type] => utility [patent_app_number] => 17/554638 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554638 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/554638
Power device embedded driver board assemblies with cooling structures and methods thereof Dec 16, 2021 Issued
Array ( [id] => 20117179 [patent_doc_number] => 12366882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Field programmable platform array [patent_app_type] => utility [patent_app_number] => 17/552336 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552336
Field programmable platform array Dec 14, 2021 Issued
Array ( [id] => 17692288 [patent_doc_number] => 20220199581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => MULTI-DIE PACKAGE STRUCTURE AND MULTI-DIE CO-PACKING METHOD [patent_app_type] => utility [patent_app_number] => 17/544075 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544075
MULTI-DIE PACKAGE STRUCTURE AND MULTI-DIE CO-PACKING METHOD Dec 6, 2021 Abandoned
Array ( [id] => 19597033 [patent_doc_number] => 12154887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Memory device and preparation method thereof [patent_app_type] => utility [patent_app_number] => 17/542419 [patent_app_country] => US [patent_app_date] => 2021-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9186 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542419 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542419
Memory device and preparation method thereof Dec 4, 2021 Issued
Array ( [id] => 19918610 [patent_doc_number] => 12293986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Method for forming chip packages and a chip package [patent_app_type] => utility [patent_app_number] => 17/542416 [patent_app_country] => US [patent_app_date] => 2021-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542416 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542416
Method for forming chip packages and a chip package Dec 3, 2021 Issued
Array ( [id] => 17676636 [patent_doc_number] => 20220189803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => SENSOR CONFIGURATION FOR PROCESS CONDITION MEASURING DEVICES [patent_app_type] => utility [patent_app_number] => 17/542135 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542135 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542135
SENSOR CONFIGURATION FOR PROCESS CONDITION MEASURING DEVICES Dec 2, 2021 Pending
Array ( [id] => 17660931 [patent_doc_number] => 20220181396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => Electroluminescence Display Apparatus [patent_app_type] => utility [patent_app_number] => 17/541986 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/541986
Electroluminescence display apparatus Dec 2, 2021 Issued
Array ( [id] => 17615502 [patent_doc_number] => 20220157782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => Fully Interconnected Heterogeneous Multi-layer Reconstructed Silicon Device [patent_app_type] => utility [patent_app_number] => 17/457350 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457350
Fully interconnected heterogeneous multi-layer reconstructed silicon device Dec 1, 2021 Issued
Array ( [id] => 19654422 [patent_doc_number] => 12176222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Semiconductor package with metal posts from structured leadframe [patent_app_type] => utility [patent_app_number] => 17/536538 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 40 [patent_no_of_words] => 8798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/536538
Semiconductor package with metal posts from structured leadframe Nov 28, 2021 Issued
Array ( [id] => 20204179 [patent_doc_number] => 12406964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Chip package and method of forming chip packages [patent_app_type] => utility [patent_app_number] => 17/535985 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 3553 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535985 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535985
Chip package and method of forming chip packages Nov 25, 2021 Issued
Array ( [id] => 19428303 [patent_doc_number] => 12087737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Method of forming chip package having stacked chips [patent_app_type] => utility [patent_app_number] => 17/535987 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 5326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535987 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535987
Method of forming chip package having stacked chips Nov 25, 2021 Issued
Array ( [id] => 18827693 [patent_doc_number] => 11842983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/525641 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 42 [patent_no_of_words] => 12184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525641 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525641
Semiconductor structure Nov 11, 2021 Issued
Menu