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Timothy Aberle

Examiner (ID: 10651)

Most Active Art Unit
3501
Art Unit(s)
3501
Total Applications
113
Issued Applications
106
Pending Applications
0
Abandoned Applications
7

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17854923 [patent_doc_number] => 20220284966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => STATIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/229823 [patent_app_country] => US [patent_app_date] => 2021-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229823
STATIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF Apr 12, 2021 Abandoned
Array ( [id] => 17522908 [patent_doc_number] => 20220108757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/220403 [patent_app_country] => US [patent_app_date] => 2021-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/220403
Memory device and method of operating the same Mar 31, 2021 Issued
Array ( [id] => 17431470 [patent_doc_number] => 20220059179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => TRACKING AND REFRESHING STATE METRICS IN MEMORY SUB-SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/301350 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301350
Tracking and refreshing state metrics in memory sub-systems Mar 30, 2021 Issued
Array ( [id] => 17900502 [patent_doc_number] => 20220310164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => MEMORY DEVICE PROGRAMMING TECHINIQUE USING FEWER LATCHES [patent_app_type] => utility [patent_app_number] => 17/216015 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216015 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216015
Memory device programming techinique using fewer latches Mar 28, 2021 Issued
Array ( [id] => 17941506 [patent_doc_number] => 11475965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/205375 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 13185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205375 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/205375
Memory device and operating method thereof Mar 17, 2021 Issued
Array ( [id] => 17708275 [patent_doc_number] => 20220208283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MEMORY CELL SENSING [patent_app_type] => utility [patent_app_number] => 17/199524 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199524
Memory cell sensing Mar 11, 2021 Issued
Array ( [id] => 17870454 [patent_doc_number] => 20220293191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => Dynamic Valley Searching in Solid State Drives [patent_app_type] => utility [patent_app_number] => 17/197488 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197488 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197488
Dynamic valley searching in solid state drives Mar 9, 2021 Issued
Array ( [id] => 17668132 [patent_doc_number] => 11361835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-14 [patent_title] => Countermeasure for reducing peak current during programming by optimizing timing of latch scan operations [patent_app_type] => utility [patent_app_number] => 17/188998 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 15247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17188998 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/188998
Countermeasure for reducing peak current during programming by optimizing timing of latch scan operations Feb 28, 2021 Issued
Array ( [id] => 17941507 [patent_doc_number] => 11475966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/185508 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10880 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185508 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185508
Memory device and method of operating the same Feb 24, 2021 Issued
Array ( [id] => 17893061 [patent_doc_number] => 11456040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Memory device and error correction method in memory device [patent_app_type] => utility [patent_app_number] => 17/185927 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185927 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185927
Memory device and error correction method in memory device Feb 24, 2021 Issued
Array ( [id] => 16904528 [patent_doc_number] => 20210183444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/180283 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180283 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180283
Resistive random access memory device Feb 18, 2021 Issued
Array ( [id] => 16872110 [patent_doc_number] => 20210165577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => SENSING OPERATIONS IN MEMORY [patent_app_type] => utility [patent_app_number] => 17/175155 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17175155 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/175155
SENSING OPERATIONS IN MEMORY Feb 11, 2021 Pending
Array ( [id] => 18000730 [patent_doc_number] => 11501841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Memory device and control method thereof [patent_app_type] => utility [patent_app_number] => 17/169919 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3741 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169919 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169919
Memory device and control method thereof Feb 7, 2021 Issued
Array ( [id] => 17779871 [patent_doc_number] => 20220246221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => EVALUATION OF BACKGROUND LEAKAGE TO SELECT WRITE VOLTAGE IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/167618 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167618 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167618
Evaluation of background leakage to select write voltage in memory devices Feb 3, 2021 Issued
Array ( [id] => 17652474 [patent_doc_number] => 11355210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Memory system and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/167513 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167513 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167513
Memory system and operating method thereof Feb 3, 2021 Issued
Array ( [id] => 17668121 [patent_doc_number] => 11361824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-14 [patent_title] => Memory device and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/164976 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17164976 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/164976
Memory device and operation method thereof Feb 1, 2021 Issued
Array ( [id] => 17878367 [patent_doc_number] => 11450388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Dynamic trim selection based on operating voltage levels for semiconductor devices and associated methods and systems [patent_app_type] => utility [patent_app_number] => 17/158490 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6450 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158490 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158490
Dynamic trim selection based on operating voltage levels for semiconductor devices and associated methods and systems Jan 25, 2021 Issued
Array ( [id] => 18190717 [patent_doc_number] => 11581319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Memory device having 2-transistor vertical memory cell [patent_app_type] => utility [patent_app_number] => 17/146043 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 15515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17146043 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/146043
Memory device having 2-transistor vertical memory cell Jan 10, 2021 Issued
Array ( [id] => 16965949 [patent_doc_number] => 20210217448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE [patent_app_type] => utility [patent_app_number] => 17/135174 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135174 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135174
Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die Dec 27, 2020 Issued
Array ( [id] => 19444265 [patent_doc_number] => 12094551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Modular error correction code circuitry [patent_app_type] => utility [patent_app_number] => 17/133810 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133810
MODULAR ERROR CORRECTION CODE CIRCUITRY Dec 23, 2020 Pending
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