Search

Timothy C Vanoy

Examiner (ID: 16970, Phone: (571)272-8158 , Office: P/1736 )

Most Active Art Unit
1736
Art Unit(s)
1754, 1734, 1793, 1735, 1736, 1103, 1724
Total Applications
3741
Issued Applications
3215
Pending Applications
124
Abandoned Applications
402

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18442206 [patent_doc_number] => 20230189502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR DEVICE HAVING WORD LINE EMBEDDED IN GATE TRENCH [patent_app_type] => utility [patent_app_number] => 17/549494 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549494 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549494
Semiconductor device having word line embedded in gate trench Dec 12, 2021 Issued
Array ( [id] => 18969375 [patent_doc_number] => 11903187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/547306 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10403 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547306
Semiconductor devices Dec 9, 2021 Issued
Array ( [id] => 18197494 [patent_doc_number] => 20230051013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/643277 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643277
Semiconductor device and method of manufacturing the same Dec 7, 2021 Issued
Array ( [id] => 17723327 [patent_doc_number] => 20220216049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/543191 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543191
METHOD FOR FORMING SEMICONDUCTOR STRUCTURE Dec 5, 2021 Pending
Array ( [id] => 18410590 [patent_doc_number] => 20230171943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => MEMORY DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/537544 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537544 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/537544
Memory device and method of forming the same Nov 29, 2021 Issued
Array ( [id] => 18381909 [patent_doc_number] => 20230157000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => ARRAY AND PERIPHERAL AREA MASKING [patent_app_type] => utility [patent_app_number] => 17/526356 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526356
Array and peripheral area masking Nov 14, 2021 Issued
Array ( [id] => 17418660 [patent_doc_number] => 20220053565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => NON-CONTIGUOUS CHANNEL BONDING [patent_app_type] => utility [patent_app_number] => 17/513668 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17513668 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/513668
NON-CONTIGUOUS CHANNEL BONDING Oct 27, 2021 Pending
Array ( [id] => 17986132 [patent_doc_number] => 20220352169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME [patent_app_type] => utility [patent_app_number] => 17/505361 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505361 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/505361
MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME Oct 18, 2021 Pending
Array ( [id] => 19294674 [patent_doc_number] => 12034039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Three electrode capacitor structure using spaced conductive pillars [patent_app_type] => utility [patent_app_number] => 17/451172 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451172
Three electrode capacitor structure using spaced conductive pillars Oct 17, 2021 Issued
Array ( [id] => 17373973 [patent_doc_number] => 20220029025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => RECESSED THIN-CHANNEL THIN-FILM TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/496690 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496690
Recessed thin-channel thin-film transistor Oct 6, 2021 Issued
Array ( [id] => 18876529 [patent_doc_number] => 11864374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/491971 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 8566 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491971 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491971
Semiconductor memory device Sep 30, 2021 Issued
Array ( [id] => 18952507 [patent_doc_number] => 11895825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Semiconductor device including integrated capacitor and vertical channel transistor and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/483859 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 11895 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483859 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483859
Semiconductor device including integrated capacitor and vertical channel transistor and methods of forming the same Sep 23, 2021 Issued
Array ( [id] => 17507073 [patent_doc_number] => 20220100176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 17/484183 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484183 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484183
SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM Sep 23, 2021 Pending
Array ( [id] => 18251404 [patent_doc_number] => 20230078443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/476048 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476048 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476048
Method of manufacturing semiconductor structure Sep 14, 2021 Issued
Array ( [id] => 17692428 [patent_doc_number] => 20220199721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => METHOD OF MANUFACTURING POLYCRYSTALLINE SILICON LAYER, DISPLAY DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/471055 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471055
METHOD OF MANUFACTURING POLYCRYSTALLINE SILICON LAYER, DISPLAY DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE Sep 8, 2021 Pending
Array ( [id] => 18952509 [patent_doc_number] => 11895827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Vertical non-volatile memory devices having a multi-stack structure with enhanced photolithographic alignment characteristics [patent_app_type] => utility [patent_app_number] => 17/469469 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11270 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469469
Vertical non-volatile memory devices having a multi-stack structure with enhanced photolithographic alignment characteristics Sep 7, 2021 Issued
Array ( [id] => 19231181 [patent_doc_number] => 12010832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/461051 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461051 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461051
Semiconductor memory device Aug 29, 2021 Issued
Array ( [id] => 18230087 [patent_doc_number] => 20230069081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => METHOD AND SYSTEM FOR ADJUSTING THE GAP BETWEEN A WAFER AND A TOP PLATE IN A THIN-FILM DEPOSITION PROCESS [patent_app_type] => utility [patent_app_number] => 17/461004 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461004 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461004
METHOD AND SYSTEM FOR ADJUSTING THE GAP BETWEEN A WAFER AND A TOP PLATE IN A THIN-FILM DEPOSITION PROCESS Aug 29, 2021 Pending
Array ( [id] => 17445824 [patent_doc_number] => 20220066329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => COMPENSATION METHOD FOR OVERLAY DEVIATION [patent_app_type] => utility [patent_app_number] => 17/445775 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445775 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445775
Compensation method for overlay deviation Aug 23, 2021 Issued
Array ( [id] => 19414940 [patent_doc_number] => 12080779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Capping layer for gate electrodes [patent_app_type] => utility [patent_app_number] => 17/408985 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408985 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408985
Capping layer for gate electrodes Aug 22, 2021 Issued
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