Timothy C Vanoy

Array ( [id] => 17780431 [patent_doc_number] => 20220246781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => HIGH MODULATION SPEED PIN-TYPE PHOTODIODE [patent_app_type] => utility [patent_app_number] => 17/249140 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16889194 [patent_doc_number] => 20210175391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => MICRO SEMICONDUCTOR DEVICE AND MICRO SEMICONDUCTOR DISPLAY [patent_app_type] => utility [patent_app_number] => 17/179845 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17795692 [patent_doc_number] => 20220254784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => EPITAXIAL SILICON WITHIN HORIZONTAL ACCESS DEVICES IN VERTICAL THREE DIMENSIONAL (3D) MEMORY [patent_app_type] => utility [patent_app_number] => 17/171336 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -34 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16904847 [patent_doc_number] => 20210183763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR DEVICE WITH METALLIZATION STRUCTURE ON OPPOSITE SIDES OF A SEMICONDUCTOR PORTION [patent_app_type] => utility [patent_app_number] => 17/170359 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17279734 [patent_doc_number] => 20210385932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => SEMICONDUCTOR MANUFACTURING APPARATUS AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/163945 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17163945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16850695 [patent_doc_number] => 20210151440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => Array Of Capacitors, An Array Of Memory Cells, A Method Of Forming An Array Of Capacitors, And A Method Of Forming An Array Of Memory Cells [patent_app_type] => utility [patent_app_number] => 17/159719 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16850580 [patent_doc_number] => 20210151325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => SEMICONDUCTOR DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/155660 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16981614 [patent_doc_number] => 20210225851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => Memory device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/151669 [patent_app_country] => US [patent_app_date] => 2021-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16873567 [patent_doc_number] => 20210167034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => CHIP ARRANGEMENTS [patent_app_type] => utility [patent_app_number] => 17/149741 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17661036 [patent_doc_number] => 20220181501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => SEMICONDUCTOR STRUCTURE WITH IN-DEVICE HIGH RESISTIVITY POLYCRYSTALLINE SEMICONDUCTOR ELEMENT AND METHOD [patent_app_type] => utility [patent_app_number] => 17/114554 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16778480 [patent_doc_number] => 20210115558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHOD AND SYSTEM FOR THE LOCALIZED DEPOSIT OF METAL ON A SURFACE [patent_app_type] => utility [patent_app_number] => 17/115181 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16578741 [patent_doc_number] => 20210013142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE USING GANGED CONDUCTIVE CONNECTIVE ASSEMBLY AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/035999 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5915 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17486290 [patent_doc_number] => 20220093794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => VERTICAL TRANSISTOR FLOATING BODY ONE TRANSISTOR DRAM MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/026199 [patent_app_country] => US [patent_app_date] => 2020-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16541434 [patent_doc_number] => 20200407847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => METHOD AND APPARATUS FOR PROVIDING STATION TO STATION UNIFORMITY [patent_app_type] => utility [patent_app_number] => 17/020001 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18315752 [patent_doc_number] => 11629826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => LED lamp [patent_app_type] => utility [patent_app_number] => 17/008007 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 63 [patent_no_of_words] => 5649 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17448428 [patent_doc_number] => 20220068933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => GATE DIELECTRIC REPAIR ON THREE-NODE ACCESS DEVICE FORMATION FOR VERTICAL THREE-DIMENSIONAL (3D) MEMORY [patent_app_type] => utility [patent_app_number] => 17/005862 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17005862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18403720 [patent_doc_number] => 11665880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Memory device having 2-transistor vertical memory cell and a common plate [patent_app_type] => utility [patent_app_number] => 17/003037 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 17217 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16677536 [patent_doc_number] => 20210066302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/003054 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17941792 [patent_doc_number] => 11476252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Memory device having 2-transistor vertical memory cell and shared channel region [patent_app_type] => utility [patent_app_number] => 17/003019 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16677430 [patent_doc_number] => 20210066196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE [patent_app_type] => utility [patent_app_number] => 17/003065 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003065 [rel_patent_id] =>[rel_patent_doc_number] =>)