
Timothy P. Callahan
Director (ID: 14944, Phone: (571)272-4066 , Office: P/2400 )
| Most Active Art Unit | 2504 |
| Art Unit(s) | 2504, 2816, 2899 |
| Total Applications | 793 |
| Issued Applications | 652 |
| Pending Applications | 7 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2778503
[patent_doc_number] => 05132554
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-21
[patent_title] => 'Clock generating apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/613696
[patent_app_country] => US
[patent_app_date] => 1990-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 21
[patent_no_of_words] => 9098
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/132/05132554.pdf
[firstpage_image] =>[orig_patent_app_number] => 613696
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/613696 | Clock generating apparatus | Nov 28, 1990 | Issued |
Array
(
[id] => 2852178
[patent_doc_number] => 05111083
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-05-05
[patent_title] => 'Detection circuit for detecting a predetermined signal from a composite signal'
[patent_app_type] => 1
[patent_app_number] => 7/620185
[patent_app_country] => US
[patent_app_date] => 1990-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3519
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/111/05111083.pdf
[firstpage_image] =>[orig_patent_app_number] => 620185
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/620185 | Detection circuit for detecting a predetermined signal from a composite signal | Nov 28, 1990 | Issued |
| 07/611224 | META-STABLE RESISTANT SIGNAL DETECTOR | Nov 8, 1990 | Abandoned |
| 07/610876 | DIGITAL TIMING DISCRIMINATOR | Nov 8, 1990 | Abandoned |
Array
(
[id] => 2780739
[patent_doc_number] => 05151625
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-29
[patent_title] => 'High frequency BiMOS linear V-I converter, voltage multiplier, mixer'
[patent_app_type] => 1
[patent_app_number] => 7/610233
[patent_app_country] => US
[patent_app_date] => 1990-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3876
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/151/05151625.pdf
[firstpage_image] =>[orig_patent_app_number] => 610233
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/610233 | High frequency BiMOS linear V-I converter, voltage multiplier, mixer | Nov 7, 1990 | Issued |
Array
(
[id] => 2863614
[patent_doc_number] => 05149988
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-22
[patent_title] => 'BICMOS positive supply voltage reference'
[patent_app_type] => 1
[patent_app_number] => 7/610724
[patent_app_country] => US
[patent_app_date] => 1990-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1574
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/149/05149988.pdf
[firstpage_image] =>[orig_patent_app_number] => 610724
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/610724 | BICMOS positive supply voltage reference | Nov 6, 1990 | Issued |
Array
(
[id] => 2824740
[patent_doc_number] => 05168177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-01
[patent_title] => 'Programmable logic device with observability and preloadability for buried state registers'
[patent_app_type] => 1
[patent_app_number] => 7/603817
[patent_app_country] => US
[patent_app_date] => 1990-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 11786
[patent_no_of_claims] => 72
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/168/05168177.pdf
[firstpage_image] =>[orig_patent_app_number] => 603817
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/603817 | Programmable logic device with observability and preloadability for buried state registers | Oct 24, 1990 | Issued |
Array
(
[id] => 2675816
[patent_doc_number] => 05073732
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-17
[patent_title] => 'Limiter circuit for alternating voltages'
[patent_app_type] => 1
[patent_app_number] => 7/603975
[patent_app_country] => US
[patent_app_date] => 1990-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1841
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/073/05073732.pdf
[firstpage_image] =>[orig_patent_app_number] => 603975
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/603975 | Limiter circuit for alternating voltages | Oct 22, 1990 | Issued |
Array
(
[id] => 2806306
[patent_doc_number] => 05124569
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-23
[patent_title] => 'Digital phase-lock loop system with analog voltage controlled oscillator'
[patent_app_type] => 1
[patent_app_number] => 7/599460
[patent_app_country] => US
[patent_app_date] => 1990-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 10326
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/124/05124569.pdf
[firstpage_image] =>[orig_patent_app_number] => 599460
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/599460 | Digital phase-lock loop system with analog voltage controlled oscillator | Oct 17, 1990 | Issued |
| 07/595518 | VARIABLE SELF-CORRECTING DIGITAL DELAY CIRCUIT | Oct 10, 1990 | Abandoned |
Array
(
[id] => 2791177
[patent_doc_number] => 05155396
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-13
[patent_title] => 'Integrated interface circuit for processing the signal supplied by a capacitive sensor'
[patent_app_type] => 1
[patent_app_number] => 7/592169
[patent_app_country] => US
[patent_app_date] => 1990-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2123
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/155/05155396.pdf
[firstpage_image] =>[orig_patent_app_number] => 592169
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/592169 | Integrated interface circuit for processing the signal supplied by a capacitive sensor | Oct 2, 1990 | Issued |
Array
(
[id] => 2807935
[patent_doc_number] => 05124656
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-23
[patent_title] => 'Adaptive estimation of phase or delay for both leading and lagging phase shifts'
[patent_app_type] => 1
[patent_app_number] => 7/589355
[patent_app_country] => US
[patent_app_date] => 1990-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3447
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/124/05124656.pdf
[firstpage_image] =>[orig_patent_app_number] => 589355
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/589355 | Adaptive estimation of phase or delay for both leading and lagging phase shifts | Sep 27, 1990 | Issued |
Array
(
[id] => 2806777
[patent_doc_number] => 05124593
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-23
[patent_title] => 'Continuous-time filter tuning circuit and method'
[patent_app_type] => 1
[patent_app_number] => 7/588201
[patent_app_country] => US
[patent_app_date] => 1990-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3741
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/124/05124593.pdf
[firstpage_image] =>[orig_patent_app_number] => 588201
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/588201 | Continuous-time filter tuning circuit and method | Sep 25, 1990 | Issued |
Array
(
[id] => 2873971
[patent_doc_number] => 05162669
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-10
[patent_title] => 'Semiconductor switch including a device for measuring a depletion layer temperature of the switch'
[patent_app_type] => 1
[patent_app_number] => 7/588018
[patent_app_country] => US
[patent_app_date] => 1990-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2309
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 302
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/162/05162669.pdf
[firstpage_image] =>[orig_patent_app_number] => 588018
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/588018 | Semiconductor switch including a device for measuring a depletion layer temperature of the switch | Sep 24, 1990 | Issued |
Array
(
[id] => 2795326
[patent_doc_number] => 05103123
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-07
[patent_title] => 'Phase detector having all NPN transistors'
[patent_app_type] => 1
[patent_app_number] => 7/583756
[patent_app_country] => US
[patent_app_date] => 1990-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3365
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 195
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/103/05103123.pdf
[firstpage_image] =>[orig_patent_app_number] => 583756
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/583756 | Phase detector having all NPN transistors | Sep 16, 1990 | Issued |
Array
(
[id] => 2972751
[patent_doc_number] => 05202589
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-13
[patent_title] => 'Apparatus for detecting the condition of switches in one transmission line'
[patent_app_type] => 1
[patent_app_number] => 7/549009
[patent_app_country] => US
[patent_app_date] => 1990-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1173
[patent_no_of_claims] => 17
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[patent_words_short_claim] => 325
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/202/05202589.pdf
[firstpage_image] =>[orig_patent_app_number] => 549009
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/549009 | Apparatus for detecting the condition of switches in one transmission line | Sep 12, 1990 | Issued |
Array
(
[id] => 2795431
[patent_doc_number] => 05136253
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-04
[patent_title] => 'Phase comparator having two different phase comparison characteristics'
[patent_app_type] => 1
[patent_app_number] => 7/581304
[patent_app_country] => US
[patent_app_date] => 1990-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5085
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/136/05136253.pdf
[firstpage_image] =>[orig_patent_app_number] => 581304
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/581304 | Phase comparator having two different phase comparison characteristics | Sep 11, 1990 | Issued |
Array
(
[id] => 2818200
[patent_doc_number] => 05079453
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-07
[patent_title] => 'Slope compensation circuit for stabilizing current mode converters'
[patent_app_type] => 1
[patent_app_number] => 7/577350
[patent_app_country] => US
[patent_app_date] => 1990-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/079/05079453.pdf
[firstpage_image] =>[orig_patent_app_number] => 577350
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/577350 | Slope compensation circuit for stabilizing current mode converters | Sep 3, 1990 | Issued |
Array
(
[id] => 2792975
[patent_doc_number] => 05101118
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-31
[patent_title] => 'Synchronization compensating circuit for use in scanning type display circuit'
[patent_app_type] => 1
[patent_app_number] => 7/574872
[patent_app_country] => US
[patent_app_date] => 1990-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4193
[patent_no_of_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/101/05101118.pdf
[firstpage_image] =>[orig_patent_app_number] => 574872
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/574872 | Synchronization compensating circuit for use in scanning type display circuit | Aug 29, 1990 | Issued |
Array
(
[id] => 2718707
[patent_doc_number] => 05053651
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-01
[patent_title] => 'Deglitched digital mixer circuit'
[patent_app_type] => 1
[patent_app_number] => 7/576134
[patent_app_country] => US
[patent_app_date] => 1990-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/053/05053651.pdf
[firstpage_image] =>[orig_patent_app_number] => 576134
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/576134 | Deglitched digital mixer circuit | Aug 27, 1990 | Issued |