
Timothy P. Callahan
Director (ID: 14944, Phone: (571)272-4066 , Office: P/2400 )
| Most Active Art Unit | 2504 |
| Art Unit(s) | 2504, 2816, 2899 |
| Total Applications | 793 |
| Issued Applications | 652 |
| Pending Applications | 7 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3082446
[patent_doc_number] => 05365384
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-15
[patent_title] => 'Video tape recorder having automatic index scan method and picture-in-picture function'
[patent_app_type] => 1
[patent_app_number] => 7/701759
[patent_app_country] => US
[patent_app_date] => 1991-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 5314
[patent_no_of_claims] => 17
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[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/365/05365384.pdf
[firstpage_image] =>[orig_patent_app_number] => 701759
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/701759 | Video tape recorder having automatic index scan method and picture-in-picture function | May 16, 1991 | Issued |
Array
(
[id] => 3108164
[patent_doc_number] => 05319604
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-07
[patent_title] => 'Circuitry and method for selectively switching negative voltages in CMOS integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 7/697172
[patent_app_country] => US
[patent_app_date] => 1991-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4164
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/319/05319604.pdf
[firstpage_image] =>[orig_patent_app_number] => 697172
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/697172 | Circuitry and method for selectively switching negative voltages in CMOS integrated circuits | May 7, 1991 | Issued |
Array
(
[id] => 2978538
[patent_doc_number] => 05182468
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-26
[patent_title] => 'Current limiting clamp circuit'
[patent_app_type] => 1
[patent_app_number] => 7/696380
[patent_app_country] => US
[patent_app_date] => 1991-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4411
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[pdf_file] => patents/05/182/05182468.pdf
[firstpage_image] =>[orig_patent_app_number] => 696380
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/696380 | Current limiting clamp circuit | May 5, 1991 | Issued |
Array
(
[id] => 2790335
[patent_doc_number] => 05093584
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-03
[patent_title] => 'Self calibrating timing circuit'
[patent_app_type] => 1
[patent_app_number] => 7/681626
[patent_app_country] => US
[patent_app_date] => 1991-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2653
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 176
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/093/05093584.pdf
[firstpage_image] =>[orig_patent_app_number] => 681626
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/681626 | Self calibrating timing circuit | May 5, 1991 | Issued |
Array
(
[id] => 2777714
[patent_doc_number] => 05075572
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-24
[patent_title] => 'Detector and integrated circuit device including charge pump circuits for high load conditions'
[patent_app_type] => 1
[patent_app_number] => 7/696982
[patent_app_country] => US
[patent_app_date] => 1991-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3165
[patent_no_of_claims] => 6
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[pdf_file] => patents/05/075/05075572.pdf
[firstpage_image] =>[orig_patent_app_number] => 696982
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/696982 | Detector and integrated circuit device including charge pump circuits for high load conditions | May 1, 1991 | Issued |
Array
(
[id] => 2834837
[patent_doc_number] => 05099155
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-24
[patent_title] => 'Active element filter network'
[patent_app_type] => 1
[patent_app_number] => 7/690162
[patent_app_country] => US
[patent_app_date] => 1991-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2600
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[pdf_file] => patents/05/099/05099155.pdf
[firstpage_image] =>[orig_patent_app_number] => 690162
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/690162 | Active element filter network | Apr 21, 1991 | Issued |
Array
(
[id] => 2899568
[patent_doc_number] => 05184027
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-02
[patent_title] => 'Clock signal supply system'
[patent_app_type] => 1
[patent_app_number] => 7/688696
[patent_app_country] => US
[patent_app_date] => 1991-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 51
[patent_no_of_words] => 15212
[patent_no_of_claims] => 21
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[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/184/05184027.pdf
[firstpage_image] =>[orig_patent_app_number] => 688696
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/688696 | Clock signal supply system | Apr 21, 1991 | Issued |
Array
(
[id] => 2896952
[patent_doc_number] => 05270583
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-14
[patent_title] => 'Impedance control circuit for a semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 7/687188
[patent_app_country] => US
[patent_app_date] => 1991-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 3488
[patent_no_of_claims] => 4
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[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/270/05270583.pdf
[firstpage_image] =>[orig_patent_app_number] => 687188
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/687188 | Impedance control circuit for a semiconductor substrate | Apr 17, 1991 | Issued |
Array
(
[id] => 3458409
[patent_doc_number] => 05378939
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-03
[patent_title] => 'Gallium arsenide monolithically integrated sampling head using equivalent time sampling having a bandwidth greater than 100 Ghz'
[patent_app_type] => 1
[patent_app_number] => 7/686916
[patent_app_country] => US
[patent_app_date] => 1991-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_no_of_words] => 23325
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[pdf_file] => patents/05/378/05378939.pdf
[firstpage_image] =>[orig_patent_app_number] => 686916
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/686916 | Gallium arsenide monolithically integrated sampling head using equivalent time sampling having a bandwidth greater than 100 Ghz | Apr 15, 1991 | Issued |
Array
(
[id] => 2795197
[patent_doc_number] => 05103116
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-07
[patent_title] => 'CMOS single phase registers'
[patent_app_type] => 1
[patent_app_number] => 7/685598
[patent_app_country] => US
[patent_app_date] => 1991-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3171
[patent_no_of_claims] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/103/05103116.pdf
[firstpage_image] =>[orig_patent_app_number] => 685598
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/685598 | CMOS single phase registers | Apr 14, 1991 | Issued |
Array
(
[id] => 2686017
[patent_doc_number] => 05045728
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-03
[patent_title] => 'Trinary to binary level conversion circuit'
[patent_app_type] => 1
[patent_app_number] => 7/683581
[patent_app_country] => US
[patent_app_date] => 1991-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2280
[patent_no_of_claims] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/045/05045728.pdf
[firstpage_image] =>[orig_patent_app_number] => 683581
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/683581 | Trinary to binary level conversion circuit | Apr 9, 1991 | Issued |
| 07/683163 | RATE CONTROLLED NOISE FILTER | Apr 9, 1991 | Abandoned |
| 07/682775 | ANALOG-TO--DIGITAL CONVERTER LATCH CIRCUIT | Apr 8, 1991 | Abandoned |
Array
(
[id] => 2788886
[patent_doc_number] => 05142171
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-25
[patent_title] => 'Integrated circuit for high side driving of an inductive load'
[patent_app_type] => 1
[patent_app_number] => 7/681417
[patent_app_country] => US
[patent_app_date] => 1991-04-04
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 5053
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/142/05142171.pdf
[firstpage_image] =>[orig_patent_app_number] => 681417
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/681417 | Integrated circuit for high side driving of an inductive load | Apr 3, 1991 | Issued |
Array
(
[id] => 2920541
[patent_doc_number] => 05179302
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-12
[patent_title] => 'Tunable data filter'
[patent_app_type] => 1
[patent_app_number] => 7/679626
[patent_app_country] => US
[patent_app_date] => 1991-04-03
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/179/05179302.pdf
[firstpage_image] =>[orig_patent_app_number] => 679626
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/679626 | Tunable data filter | Apr 2, 1991 | Issued |
Array
(
[id] => 2939082
[patent_doc_number] => 05196740
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-23
[patent_title] => 'Integrated circuit for analogue system'
[patent_app_type] => 1
[patent_app_number] => 7/679483
[patent_app_country] => US
[patent_app_date] => 1991-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
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[patent_no_of_words] => 6227
[patent_no_of_claims] => 21
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[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/196/05196740.pdf
[firstpage_image] =>[orig_patent_app_number] => 679483
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/679483 | Integrated circuit for analogue system | Apr 1, 1991 | Issued |
Array
(
[id] => 2882237
[patent_doc_number] => 05159278
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-27
[patent_title] => 'State machine architecture providing increased resolution of output timing'
[patent_app_type] => 1
[patent_app_number] => 7/679379
[patent_app_country] => US
[patent_app_date] => 1991-04-02
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[pdf_file] => patents/05/159/05159278.pdf
[firstpage_image] =>[orig_patent_app_number] => 679379
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/679379 | State machine architecture providing increased resolution of output timing | Apr 1, 1991 | Issued |
Array
(
[id] => 2908804
[patent_doc_number] => 05245583
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-14
[patent_title] => 'Integrated circuit memory with decoded address sustain circuitry for multiplexed address architecture and method'
[patent_app_type] => 1
[patent_app_number] => 7/679511
[patent_app_country] => US
[patent_app_date] => 1991-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4300
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/245/05245583.pdf
[firstpage_image] =>[orig_patent_app_number] => 679511
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/679511 | Integrated circuit memory with decoded address sustain circuitry for multiplexed address architecture and method | Apr 1, 1991 | Issued |
Array
(
[id] => 2806850
[patent_doc_number] => 05124597
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-23
[patent_title] => 'Timer circuit including an analog ramp generator and a CMOS counter'
[patent_app_type] => 1
[patent_app_number] => 7/678385
[patent_app_country] => US
[patent_app_date] => 1991-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 22
[patent_no_of_words] => 10564
[patent_no_of_claims] => 22
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/124/05124597.pdf
[firstpage_image] =>[orig_patent_app_number] => 678385
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/678385 | Timer circuit including an analog ramp generator and a CMOS counter | Mar 31, 1991 | Issued |
| 07/678247 | ANALOG STANDARD CELL | Mar 31, 1991 | Abandoned |