Search

Titus Wong

Examiner (ID: 13324, Phone: (571)270-1627 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2181, 2185, 2184
Total Applications
690
Issued Applications
506
Pending Applications
52
Abandoned Applications
146

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13728917 [patent_doc_number] => 20180368926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => SYSTEM AND METHOD FOR ADVANCED DATA MANAGEMENT WITH VIDEO ENABLED SOFTWARE TOOLS FOR VIDEO BROADCASTING ENVIRONMENTS [patent_app_type] => utility [patent_app_number] => 15/657080 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15657080 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/657080
System and method for advanced data management with video enabled software tools for video broadcasting environments Jul 20, 2017 Issued
Array ( [id] => 12460305 [patent_doc_number] => 09985977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Direct cache access for network input/output devices [patent_app_type] => utility [patent_app_number] => 15/651274 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651274
Direct cache access for network input/output devices Jul 16, 2017 Issued
Array ( [id] => 16551801 [patent_doc_number] => 10884961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Dynamic termination circuit, semiconductor apparatus and system including the same [patent_app_type] => utility [patent_app_number] => 15/642639 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5034 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15642639 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/642639
Dynamic termination circuit, semiconductor apparatus and system including the same Jul 5, 2017 Issued
Array ( [id] => 12160852 [patent_doc_number] => 20180032118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'CONTROL METHOD, EXTENSION DEVICE, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 15/642640 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9074 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15642640 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/642640
CONTROL METHOD, EXTENSION DEVICE, AND RECORDING MEDIUM Jul 5, 2017 Abandoned
Array ( [id] => 13186079 [patent_doc_number] => 10108560 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-23 [patent_title] => Ethernet-leveraged hyper-converged infrastructure [patent_app_type] => utility [patent_app_number] => 15/624537 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624537 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/624537
Ethernet-leveraged hyper-converged infrastructure Jun 14, 2017 Issued
Array ( [id] => 11838751 [patent_doc_number] => 20170220471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'Control of Pre-Fetch Traffic' [patent_app_type] => utility [patent_app_number] => 15/488649 [patent_app_country] => US [patent_app_date] => 2017-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7819 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15488649 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/488649
Control of pre-fetch traffic Apr 16, 2017 Issued
Array ( [id] => 17283154 [patent_doc_number] => 11200183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Scalable interrupt virtualization for input/output devices [patent_app_type] => utility [patent_app_number] => 16/493148 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 16476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16493148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/493148
Scalable interrupt virtualization for input/output devices Mar 30, 2017 Issued
Array ( [id] => 11759302 [patent_doc_number] => 20170206171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'Collapsed Address Translation With Multiple Page Sizes' [patent_app_type] => utility [patent_app_number] => 15/475718 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10777 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475718 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475718
Collapsed address translation with multiple page sizes Mar 30, 2017 Issued
Array ( [id] => 13449241 [patent_doc_number] => 20180276163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => USE OF PHYSICAL BLOCKS TO DEVELOP MICROSERVICES [patent_app_type] => utility [patent_app_number] => 15/464963 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15464963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/464963
Use of physical blocks to develop microservices Mar 20, 2017 Issued
Array ( [id] => 11754513 [patent_doc_number] => 09712544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Direct cache access for network input/output devices' [patent_app_type] => utility [patent_app_number] => 15/434342 [patent_app_country] => US [patent_app_date] => 2017-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15434342 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/434342
Direct cache access for network input/output devices Feb 15, 2017 Issued
Array ( [id] => 11653968 [patent_doc_number] => 20170149874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'Load Balanced Network File Accesses' [patent_app_type] => utility [patent_app_number] => 15/427510 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6685 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15427510 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/427510
Load balanced network file accesses Feb 7, 2017 Issued
Array ( [id] => 17757401 [patent_doc_number] => 11397693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Peripheral device, system including the peripheral device and method [patent_app_type] => utility [patent_app_number] => 16/069513 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6160 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16069513 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/069513
Peripheral device, system including the peripheral device and method Jan 22, 2017 Issued
Array ( [id] => 14642569 [patent_doc_number] => 10366029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Data transceiving method and device [patent_app_type] => utility [patent_app_number] => 15/411046 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15940 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411046 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/411046
Data transceiving method and device Jan 19, 2017 Issued
Array ( [id] => 13304555 [patent_doc_number] => 20180203814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => TEST PENDING EXTERNAL INTERRUPTION INSTRUCTION [patent_app_type] => utility [patent_app_number] => 15/409592 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15409592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/409592
Test pending external interruption instruction Jan 18, 2017 Issued
Array ( [id] => 11709041 [patent_doc_number] => 20170177540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Interface with Variable Data Rate' [patent_app_type] => utility [patent_app_number] => 15/393234 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7276 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15393234 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/393234
Interface with variable data rate Dec 27, 2016 Issued
Array ( [id] => 11665291 [patent_doc_number] => 20170154010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'SYSTEMS AND METHODS FOR TRANSMITTING AN ACCESS REQUEST VIA A FLEXIBLE REGISTER ACCESS BUS' [patent_app_type] => utility [patent_app_number] => 15/364503 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364503 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364503
Systems and methods for transmitting an access request via a flexible register access bus Nov 29, 2016 Issued
Array ( [id] => 16130173 [patent_doc_number] => 10698847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => One wire bus to RFFE translation system [patent_app_type] => utility [patent_app_number] => 15/365295 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 41802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365295 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365295
One wire bus to RFFE translation system Nov 29, 2016 Issued
Array ( [id] => 15545271 [patent_doc_number] => 10572416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-25 [patent_title] => Efficient signaling scheme for high-speed ultra short reach interfaces [patent_app_type] => utility [patent_app_number] => 15/364030 [patent_app_country] => US [patent_app_date] => 2016-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364030 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364030
Efficient signaling scheme for high-speed ultra short reach interfaces Nov 28, 2016 Issued
Array ( [id] => 17605995 [patent_doc_number] => 11334484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Optimizing write and wear performance for a memory [patent_app_type] => utility [patent_app_number] => 15/340826 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340826
Optimizing write and wear performance for a memory Oct 31, 2016 Issued
Array ( [id] => 14952981 [patent_doc_number] => 10437755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Techniques for handling interrupts in a processing unit using virtual processor thread groups [patent_app_type] => utility [patent_app_number] => 15/334951 [patent_app_country] => US [patent_app_date] => 2016-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 7937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15334951 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/334951
Techniques for handling interrupts in a processing unit using virtual processor thread groups Oct 25, 2016 Issued
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