
Titus Wong
Examiner (ID: 19525)
| Most Active Art Unit | 2184 |
| Art Unit(s) | 2181, 2185, 2184 |
| Total Applications | 695 |
| Issued Applications | 511 |
| Pending Applications | 51 |
| Abandoned Applications | 146 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12008826
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[patent_issue_date] => 2017-10-31
[patent_title] => 'Apparatus and method for cloning and snapshotting in multi-dimensional to linear address space translation'
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[patent_app_number] => 14/091211
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Array
(
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[patent_doc_number] => 09619402
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[patent_kind] => B1
[patent_issue_date] => 2017-04-11
[patent_title] => 'Method and apparatus for optimizing translation of a virtual memory address into a physical memory address in a processor having virtual memory'
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Array
(
[id] => 9372371
[patent_doc_number] => 20140082244
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[patent_issue_date] => 2014-03-20
[patent_title] => 'Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes'
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[patent_app_number] => 14/087953
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[patent_app_date] => 2013-11-22
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Array
(
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[patent_doc_number] => 20150143017
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[patent_issue_date] => 2015-05-21
[patent_title] => 'Memory Device Debugging on Host Platforms'
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Array
(
[id] => 9548513
[patent_doc_number] => 20140173161
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[patent_issue_date] => 2014-06-19
[patent_title] => 'MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK'
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Array
(
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[patent_issue_date] => 2014-05-20
[patent_title] => 'Automatic attachment and detachment for hub and peripheral devices'
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Array
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[patent_title] => 'Clocking for pipelined routing'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/075802 | Clocking for pipelined routing | Nov 7, 2013 | Issued |
Array
(
[id] => 14123455
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[patent_issue_date] => 2019-04-02
[patent_title] => Reduced host data command processing
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/075905 | Reduced host data command processing | Nov 7, 2013 | Issued |
Array
(
[id] => 10242883
[patent_doc_number] => 20150127878
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[patent_issue_date] => 2015-05-07
[patent_title] => 'TUNNELED WINDOW CONNECTION FOR PROGRAMMED INPUT OUTPUT TRANSFERS OVER A SWITCH FABRIC'
[patent_app_type] => utility
[patent_app_number] => 14/073491
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/073491 | TUNNELED WINDOW CONNECTION FOR PROGRAMMED INPUT OUTPUT TRANSFERS OVER A SWITCH FABRIC | Nov 5, 2013 | Abandoned |
Array
(
[id] => 9781177
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[patent_title] => 'Process to generate various length parameters in a number of SGLS based upon the length fields of another SGL'
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Array
(
[id] => 10242865
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[patent_issue_date] => 2015-05-07
[patent_title] => 'SETTING A PCIE DEVICE ID'
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Array
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Array
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Array
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Array
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Array
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Array
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