Search

Titus Wong

Examiner (ID: 13324, Phone: (571)270-1627 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2181, 2185, 2184
Total Applications
690
Issued Applications
506
Pending Applications
52
Abandoned Applications
146

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17345861 [patent_doc_number] => 20220012192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => STORAGE DEVICE ADAPTIVELY SUPPORTING PLURALITY OF PROTOCOLS [patent_app_type] => utility [patent_app_number] => 17/448971 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448971 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448971
Storage device adaptively supporting plurality of protocols Sep 26, 2021 Issued
Array ( [id] => 18933937 [patent_doc_number] => 11886365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => DMA control circuit with quality of service indications [patent_app_type] => utility [patent_app_number] => 17/475074 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 18556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17475074 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/475074
DMA control circuit with quality of service indications Sep 13, 2021 Issued
Array ( [id] => 19391525 [patent_doc_number] => 20240281395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => Embedded-Oriented Configurable Many-Core Processor [patent_app_type] => utility [patent_app_number] => 18/682893 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18682893 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/682893
Embedded-Oriented Configurable Many-Core Processor Sep 9, 2021 Pending
Array ( [id] => 17507566 [patent_doc_number] => 20220100669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SMART STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/403862 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403862 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403862
Smart storage device using a computer express link (CXL) interface Aug 15, 2021 Issued
Array ( [id] => 17264352 [patent_doc_number] => 20210377337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => LOAD BALANCED NETWORK FILE ACCESSES [patent_app_type] => utility [patent_app_number] => 17/402834 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402834 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402834
Load balanced network file accesses Aug 15, 2021 Issued
Array ( [id] => 18015231 [patent_doc_number] => 11507529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Multi-chip module with configurable multi-mode serial link interfaces [patent_app_type] => utility [patent_app_number] => 17/397115 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6721 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397115 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397115
Multi-chip module with configurable multi-mode serial link interfaces Aug 8, 2021 Issued
Array ( [id] => 19458950 [patent_doc_number] => 12099439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Performing load and store operations of 2D arrays in a single cycle in a system on a chip [patent_app_type] => utility [patent_app_number] => 17/391468 [patent_app_country] => US [patent_app_date] => 2021-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 61 [patent_no_of_words] => 58299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391468 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/391468
Performing load and store operations of 2D arrays in a single cycle in a system on a chip Aug 1, 2021 Issued
Array ( [id] => 18166976 [patent_doc_number] => 20230033583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => PRIMARY INPUT-OUTPUT QUEUE SERVING HOST AND GUEST OPERATING SYSTEMS CONCURRENTLY [patent_app_type] => utility [patent_app_number] => 17/389925 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389925
PRIMARY INPUT-OUTPUT QUEUE SERVING HOST AND GUEST OPERATING SYSTEMS CONCURRENTLY Jul 29, 2021 Pending
Array ( [id] => 17202167 [patent_doc_number] => 20210342262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => PERIODIC FLUSH IN MEMORY COMPONENT THAT IS USING GREEDY GARBAGE COLLECTION [patent_app_type] => utility [patent_app_number] => 17/375478 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375478
Periodic flush in memory component that is using greedy garbage collection Jul 13, 2021 Issued
Array ( [id] => 18584793 [patent_doc_number] => 20230267057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => IPMI COMMAND PROCESSING METHOD AND SYSTEM FOR BMC, AND DEVICE AND MEDIUM [patent_app_type] => utility [patent_app_number] => 18/012926 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18012926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/012926
IPMI command processing method and system for BMC, and device and medium Jun 28, 2021 Issued
Array ( [id] => 19362932 [patent_doc_number] => 20240264966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => Identification of Option Cards Using Multiple Voltage Inputs [patent_app_type] => utility [patent_app_number] => 18/565950 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18565950 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/565950
Identification of Option Cards Using Multiple Voltage Inputs Jun 27, 2021 Pending
Array ( [id] => 19885613 [patent_doc_number] => 12271326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Data flow-based neural network multi-engine synchronous calculation system [patent_app_type] => utility [patent_app_number] => 18/011528 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4053 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18011528 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/011528
Data flow-based neural network multi-engine synchronous calculation system Jun 3, 2021 Issued
Array ( [id] => 18186176 [patent_doc_number] => 11576731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => System and method for advanced data management with video enabled software tools for video broadcasting environments [patent_app_type] => utility [patent_app_number] => 17/337364 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4332 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 433 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/337364
System and method for advanced data management with video enabled software tools for video broadcasting environments Jun 1, 2021 Issued
Array ( [id] => 17832310 [patent_doc_number] => 20220269614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => TREATING MAIN MEMORY AS A COLLECTION OF TAGGED CACHE LINES FOR TRACE LOGGING [patent_app_type] => utility [patent_app_number] => 17/324776 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17324776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/324776
Treating main memory as a collection of tagged cache lines for trace logging May 18, 2021 Issued
Array ( [id] => 18104322 [patent_doc_number] => 11544208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Wave pipeline including synchronous stage [patent_app_type] => utility [patent_app_number] => 17/324172 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7563 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17324172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/324172
Wave pipeline including synchronous stage May 18, 2021 Issued
Array ( [id] => 18872985 [patent_doc_number] => 11860792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Memory access handling for peripheral component interconnect devices [patent_app_type] => utility [patent_app_number] => 17/307274 [patent_app_country] => US [patent_app_date] => 2021-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7680 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307274 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/307274
Memory access handling for peripheral component interconnect devices May 3, 2021 Issued
Array ( [id] => 17947966 [patent_doc_number] => 20220334985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => ADAPTOR STORAGE SYSTEM OF AND METHOD [patent_app_type] => utility [patent_app_number] => 17/232944 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232944 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232944
Adaptor storage system of and method Apr 15, 2021 Issued
Array ( [id] => 18089825 [patent_doc_number] => 11539971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Method for parallel image processing and routing [patent_app_type] => utility [patent_app_number] => 17/221739 [patent_app_country] => US [patent_app_date] => 2021-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 19334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17221739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/221739
Method for parallel image processing and routing Apr 1, 2021 Issued
Array ( [id] => 19669685 [patent_doc_number] => 12182434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Method and apparatus for data access of NAND FLASH file, and storage medium [patent_app_type] => utility [patent_app_number] => 17/995459 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6182 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17995459 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/995459
Method and apparatus for data access of NAND FLASH file, and storage medium Mar 22, 2021 Issued
Array ( [id] => 17172615 [patent_doc_number] => 20210326285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES [patent_app_type] => utility [patent_app_number] => 17/207135 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207135 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207135
Dynamic configuration of input/output controller access lanes Mar 18, 2021 Issued
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