Search

Titus Wong

Examiner (ID: 13324, Phone: (571)270-1627 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2181, 2185, 2184
Total Applications
690
Issued Applications
506
Pending Applications
52
Abandoned Applications
146

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17861712 [patent_doc_number] => 11442870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Information processing apparatus having an integrated circuit chip with first and second communication units having address translation function [patent_app_type] => utility [patent_app_number] => 17/190750 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11128 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190750 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190750
Information processing apparatus having an integrated circuit chip with first and second communication units having address translation function Mar 2, 2021 Issued
Array ( [id] => 19028699 [patent_doc_number] => 11928056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Memory controller for allocating cache lines and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/180531 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 14801 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180531 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180531
Memory controller for allocating cache lines and method of operating the same Feb 18, 2021 Issued
Array ( [id] => 19703348 [patent_doc_number] => 12197373 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-14 [patent_title] => Test, development and deployment infrastructure for spacecube high-performance flight processors [patent_app_type] => utility [patent_app_number] => 17/173557 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173557
Test, development and deployment infrastructure for spacecube high-performance flight processors Feb 10, 2021 Issued
Array ( [id] => 16826427 [patent_doc_number] => 20210141720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => MEMORY MANAGEMENT FOR MULTIPLE PROCESS INSTANCES [patent_app_type] => utility [patent_app_number] => 17/155014 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/155014
Memory management for multiple process instances Jan 20, 2021 Issued
Array ( [id] => 18253079 [patent_doc_number] => 20230080118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => INFORMATION PROCESSING DEVICE, MASTER DEVICE, INFORMATION PROCESSING SYSTEM, NOTIFICATION METHOD, AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 17/798303 [patent_app_country] => US [patent_app_date] => 2021-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17798303 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/798303
INFORMATION PROCESSING DEVICE, MASTER DEVICE, INFORMATION PROCESSING SYSTEM, NOTIFICATION METHOD, AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM Jan 17, 2021 Abandoned
Array ( [id] => 18234900 [patent_doc_number] => 11599459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Communication gateway for communicating data frames for a motor vehicle [patent_app_type] => utility [patent_app_number] => 17/147710 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6122 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 447 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147710 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147710
Communication gateway for communicating data frames for a motor vehicle Jan 12, 2021 Issued
Array ( [id] => 18401010 [patent_doc_number] => 11663148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Performance of storage system background operations [patent_app_type] => utility [patent_app_number] => 17/138082 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138082
Performance of storage system background operations Dec 29, 2020 Issued
Array ( [id] => 16849070 [patent_doc_number] => 20210149815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => TECHNOLOGIES FOR OFFLOAD DEVICE FETCHING OF ADDRESS TRANSLATIONS [patent_app_type] => utility [patent_app_number] => 17/129496 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129496 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/129496
Technologies for offload device fetching of address translations Dec 20, 2020 Issued
Array ( [id] => 17528713 [patent_doc_number] => 11301401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-12 [patent_title] => Ball grid array storage for a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/127289 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127289
Ball grid array storage for a memory sub-system Dec 17, 2020 Issued
Array ( [id] => 16729868 [patent_doc_number] => 20210097015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE [patent_app_type] => utility [patent_app_number] => 17/121534 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121534 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121534
Extending multichip package link off package Dec 13, 2020 Issued
Array ( [id] => 17622010 [patent_doc_number] => 11341066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Cache for artificial intelligence processor [patent_app_type] => utility [patent_app_number] => 17/119387 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3564 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17119387 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/119387
Cache for artificial intelligence processor Dec 10, 2020 Issued
Array ( [id] => 18949663 [patent_doc_number] => 11892956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Performance of memory system background operations [patent_app_type] => utility [patent_app_number] => 17/111195 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13119 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111195
Performance of memory system background operations Dec 2, 2020 Issued
Array ( [id] => 17331515 [patent_doc_number] => 11221979 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => Synchronization of DMA transfers for large number of queues [patent_app_type] => utility [patent_app_number] => 17/247016 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247016
Synchronization of DMA transfers for large number of queues Nov 23, 2020 Issued
Array ( [id] => 17824599 [patent_doc_number] => 11429547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Apparatus and method for the buffered transmission of data by a controller to reduce a load on a central processing unit [patent_app_type] => utility [patent_app_number] => 17/101953 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3064 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101953 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101953
Apparatus and method for the buffered transmission of data by a controller to reduce a load on a central processing unit Nov 22, 2020 Issued
Array ( [id] => 17283144 [patent_doc_number] => 11200173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Controlling cache size and priority using machine learning techniques [patent_app_type] => utility [patent_app_number] => 17/101689 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101689
Controlling cache size and priority using machine learning techniques Nov 22, 2020 Issued
Array ( [id] => 17581276 [patent_doc_number] => 20220138131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => INPUT/OUTPUT DEVICE OPERATIONAL MODES FOR A SYSTEM WITH MEMORY POOLS [patent_app_type] => utility [patent_app_number] => 17/087221 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087221 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087221
Input/output device operational modes for a system with memory pools Nov 1, 2020 Issued
Array ( [id] => 17565245 [patent_doc_number] => 20220129394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => MANAGED NAND FLASH MEMORY REGION CONTROL AGAINST ENDURANCE HACKING [patent_app_type] => utility [patent_app_number] => 17/077503 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077503 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077503
Managed NAND flash memory region control against endurance hacking Oct 21, 2020 Issued
Array ( [id] => 17550272 [patent_doc_number] => 20220121614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SYSTEM ON CHIP COMPRISING A PLURALITY OF CENTRAL PROCESSING UNITS [patent_app_type] => utility [patent_app_number] => 17/071996 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071996 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/071996
System on chip comprising a plurality of central processing units whose mailboxes are set in tightly-coupled memories Oct 14, 2020 Issued
Array ( [id] => 17977222 [patent_doc_number] => 11494081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => System and method for using telemetry data to change operation of storage middleware client of a data center [patent_app_type] => utility [patent_app_number] => 17/066566 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066566 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/066566
System and method for using telemetry data to change operation of storage middleware client of a data center Oct 8, 2020 Issued
Array ( [id] => 17415866 [patent_doc_number] => 20220050770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => METHOD AND SYSTEM FOR PERFORMING READ/WRITE OPERATION WITHIN A COMPUTING SYSTEM HOSTING NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/060686 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/060686
Method and system for performing read/write operation within a computing system hosting non-volatile memory Sep 30, 2020 Issued
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