Search

Toan K. Le

Examiner (ID: 18217)

Most Active Art Unit
2824
Art Unit(s)
2825, 2824, 3722
Total Applications
1303
Issued Applications
1255
Pending Applications
5
Abandoned Applications
46

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14163547 [patent_doc_number] => 20190108876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => MULTIPORT MEMORY, MEMORY MACRO AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/214220 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214220
Multiport memory, memory macro and semiconductor device Dec 9, 2018 Issued
Array ( [id] => 14676067 [patent_doc_number] => 20190237148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHODS FOR OPERATING A SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/209115 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16209115 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/209115
Semiconductor memory device and methods for operating a semiconductor memory device Dec 3, 2018 Issued
Array ( [id] => 15153899 [patent_doc_number] => 20190355427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/208239 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/208239
Nonvolatile memory device and memory system including the nonvolatile memory device Dec 2, 2018 Issued
Array ( [id] => 17470331 [patent_doc_number] => 11276814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Spin-orbit torque magnetic random access memory [patent_app_type] => utility [patent_app_number] => 16/757559 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3200 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16757559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/757559
Spin-orbit torque magnetic random access memory Nov 27, 2018 Issued
Array ( [id] => 15388807 [patent_doc_number] => 10535602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Reduced area eFuse cell structure [patent_app_type] => utility [patent_app_number] => 16/202708 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202708 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202708
Reduced area eFuse cell structure Nov 27, 2018 Issued
Array ( [id] => 14078911 [patent_doc_number] => 20190088343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => APPARATUS CONFIGURED TO PROGRAM MEMORY CELLS USING AN INTERMEDIATE LEVEL FOR MULTIPLE DATA STATES [patent_app_type] => utility [patent_app_number] => 16/186739 [patent_app_country] => US [patent_app_date] => 2018-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11926 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/186739
Apparatus configured to program memory cells using an intermediate level for multiple data states Nov 11, 2018 Issued
Array ( [id] => 14475103 [patent_doc_number] => 20190189197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/176299 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176299 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176299
Semiconductor memory device Oct 30, 2018 Issued
Array ( [id] => 13962769 [patent_doc_number] => 20190057729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => APPARATUSES, CIRCUITS, AND METHODS FOR BIASING SIGNAL LINES [patent_app_type] => utility [patent_app_number] => 16/165732 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165732 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165732
Apparatuses, circuits, and methods for biasing signal lines Oct 18, 2018 Issued
Array ( [id] => 13875833 [patent_doc_number] => 20190034257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => APPARATUSES AND METHODS FOR COMPARING A CURRENT REPRESENTATIVE OF A NUMBER OF FAILING MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/148947 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148947 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148947
Apparatuses and methods for comparing a current representative of a number of failing memory cells Sep 30, 2018 Issued
Array ( [id] => 14508869 [patent_doc_number] => 20190198089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => INTEGRATED CIRCUIT CHIP [patent_app_type] => utility [patent_app_number] => 16/127845 [patent_app_country] => US [patent_app_date] => 2018-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16127845 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/127845
Integrated circuit chip Sep 10, 2018 Issued
Array ( [id] => 13785681 [patent_doc_number] => 20190006379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/126231 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126231 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126231
Memory system and method for controlling nonvolatile memory Sep 9, 2018 Issued
Array ( [id] => 14676071 [patent_doc_number] => 20190237150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/124927 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124927 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/124927
Memory system and operating method thereof Sep 6, 2018 Issued
Array ( [id] => 14676051 [patent_doc_number] => 20190237140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SINGLE POLY MULTI TIME PROGRAM CELL AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/123725 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16123725 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/123725
Single poly multi time program cell and method of operating the same Sep 5, 2018 Issued
Array ( [id] => 15401165 [patent_doc_number] => 10541244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-21 [patent_title] => Layout pattern for static random access memory [patent_app_type] => utility [patent_app_number] => 16/121609 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5278 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121609 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121609
Layout pattern for static random access memory Sep 3, 2018 Issued
Array ( [id] => 16356515 [patent_doc_number] => 10797033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Apparatuses and methods for high sensitivity TSV resistance measurement circuit [patent_app_type] => utility [patent_app_number] => 16/121377 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12986 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121377
Apparatuses and methods for high sensitivity TSV resistance measurement circuit Sep 3, 2018 Issued
Array ( [id] => 14475091 [patent_doc_number] => 20190189191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => LAYOUT STRUCTURE OF A BIT LINE SENSE AMPLIFIER IN A SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/116079 [patent_app_country] => US [patent_app_date] => 2018-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/116079
Layout structure of a bit line sense amplifier in a semiconductor memory device Aug 28, 2018 Issued
Array ( [id] => 14721921 [patent_doc_number] => 20190252024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/111915 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111915 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/111915
Memory system Aug 23, 2018 Issued
Array ( [id] => 16293276 [patent_doc_number] => 10770129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Pseudo-channeled DRAM [patent_app_type] => utility [patent_app_number] => 16/106911 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7302 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106911 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106911
Pseudo-channeled DRAM Aug 20, 2018 Issued
Array ( [id] => 15889115 [patent_doc_number] => 10650906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Memory bypass function for a memory [patent_app_type] => utility [patent_app_number] => 16/059477 [patent_app_country] => US [patent_app_date] => 2018-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6898 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16059477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/059477
Memory bypass function for a memory Aug 8, 2018 Issued
Array ( [id] => 13600023 [patent_doc_number] => 20180351560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => SINGLE-LOCK DELAY LOCKED LOOP WITH CYCLE COUNTER AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/059136 [patent_app_country] => US [patent_app_date] => 2018-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16059136 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/059136
Single-lock delay locked loop with cycle counter and method therefor Aug 8, 2018 Issued
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