Search

Toan K. Le

Examiner (ID: 18217)

Most Active Art Unit
2824
Art Unit(s)
2825, 2824, 3722
Total Applications
1303
Issued Applications
1255
Pending Applications
5
Abandoned Applications
46

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14295635 [patent_doc_number] => 10287935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Virtual filter condition sensor [patent_app_type] => utility [patent_app_number] => 15/965255 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15965255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/965255
Virtual filter condition sensor Apr 26, 2018 Issued
Array ( [id] => 15580157 [patent_doc_number] => 10580470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Spin current magnetization rotational element, magnetoresistance effect element, and magnetic memory [patent_app_type] => utility [patent_app_number] => 15/956523 [patent_app_country] => US [patent_app_date] => 2018-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 12978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15956523 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/956523
Spin current magnetization rotational element, magnetoresistance effect element, and magnetic memory Apr 17, 2018 Issued
Array ( [id] => 14984649 [patent_doc_number] => 10446244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-15 [patent_title] => Adjusting voltage on adjacent word line during verify of memory cells on selected word line in multi-pass programming [patent_app_type] => utility [patent_app_number] => 15/948761 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 15333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948761 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/948761
Adjusting voltage on adjacent word line during verify of memory cells on selected word line in multi-pass programming Apr 8, 2018 Issued
Array ( [id] => 13270815 [patent_doc_number] => 10147494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Apparatus configured to program memory cells using an intermediate level for multiple data states [patent_app_type] => utility [patent_app_number] => 15/933498 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/933498
Apparatus configured to program memory cells using an intermediate level for multiple data states Mar 22, 2018 Issued
Array ( [id] => 15856759 [patent_doc_number] => 10643672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Memory with non-volatile configurations for efficient power management and operation of the same [patent_app_type] => utility [patent_app_number] => 15/933687 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4177 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933687 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/933687
Memory with non-volatile configurations for efficient power management and operation of the same Mar 22, 2018 Issued
Array ( [id] => 13950861 [patent_doc_number] => 10211209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle [patent_app_type] => utility [patent_app_number] => 15/933897 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933897 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/933897
Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle Mar 22, 2018 Issued
Array ( [id] => 14903773 [patent_doc_number] => 20190295652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => PROGRAM SCHEME IN 3D NAND FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 15/926217 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15926217 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/926217
Program scheme in 3D NAND flash memory Mar 19, 2018 Issued
Array ( [id] => 14954745 [patent_doc_number] => 10438649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Systems and methods for conserving power in signal quality operations for memory devices [patent_app_type] => utility [patent_app_number] => 15/924857 [patent_app_country] => US [patent_app_date] => 2018-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 8589 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15924857 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/924857
Systems and methods for conserving power in signal quality operations for memory devices Mar 18, 2018 Issued
Array ( [id] => 14525505 [patent_doc_number] => 10340023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-02 [patent_title] => Method and system for determining bit values in non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/923247 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15923247 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/923247
Method and system for determining bit values in non-volatile memory Mar 15, 2018 Issued
Array ( [id] => 14671511 [patent_doc_number] => 10373670 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-06 [patent_title] => Memory device with an array timer mechanism [patent_app_type] => utility [patent_app_number] => 15/923235 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15923235 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/923235
Memory device with an array timer mechanism Mar 15, 2018 Issued
Array ( [id] => 13667211 [patent_doc_number] => 10163783 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-25 [patent_title] => Reduced area efuse cell structure [patent_app_type] => utility [patent_app_number] => 15/922439 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922439 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/922439
Reduced area efuse cell structure Mar 14, 2018 Issued
Array ( [id] => 14784367 [patent_doc_number] => 20190267081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => Resistive Change Element Cells Sharing Selection Devices [patent_app_type] => utility [patent_app_number] => 15/906661 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15906661 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/906661
Resistive change element cells sharing selection devices Feb 26, 2018 Issued
Array ( [id] => 14672453 [patent_doc_number] => 10374150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Magnetic memory device [patent_app_type] => utility [patent_app_number] => 15/905271 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 44 [patent_no_of_words] => 20651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15905271 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/905271
Magnetic memory device Feb 25, 2018 Issued
Array ( [id] => 13378709 [patent_doc_number] => 20180240896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => MAGNETO-ELECTRIC LOGIC DEVICES USING SEMICONDUCTOR CHANNEL WITH LARGE SPIN-ORBIT COUPLING [patent_app_type] => utility [patent_app_number] => 15/898457 [patent_app_country] => US [patent_app_date] => 2018-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898457 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/898457
Magneto-electric logic devices using semiconductor channel with large spin-orbit coupling Feb 16, 2018 Issued
Array ( [id] => 13242495 [patent_doc_number] => 10134454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Apparatuses, circuits, and methods for biasing signal lines [patent_app_type] => utility [patent_app_number] => 15/895290 [patent_app_country] => US [patent_app_date] => 2018-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15895290 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/895290
Apparatuses, circuits, and methods for biasing signal lines Feb 12, 2018 Issued
Array ( [id] => 13282893 [patent_doc_number] => 10153037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Multiport memory, memory macro and semiconductor device [patent_app_type] => utility [patent_app_number] => 15/885449 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7596 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885449 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/885449
Multiport memory, memory macro and semiconductor device Jan 30, 2018 Issued
Array ( [id] => 13769007 [patent_doc_number] => 10176850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Method and apparatus for memory power and/or area reduction [patent_app_type] => utility [patent_app_number] => 15/880913 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 11491 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880913 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880913
Method and apparatus for memory power and/or area reduction Jan 25, 2018 Issued
Array ( [id] => 13995315 [patent_doc_number] => 20190066815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => APPARATUS AND METHOD FOR MEASURING PERFORMANCE OF MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 15/879455 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879455 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879455
Apparatus and method for measuring performance of memory array Jan 24, 2018 Issued
Array ( [id] => 14616495 [patent_doc_number] => 10360951 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-23 [patent_title] => Internal write adjust for a memory device [patent_app_type] => utility [patent_app_number] => 15/875651 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15875651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/875651
Internal write adjust for a memory device Jan 18, 2018 Issued
Array ( [id] => 13392277 [patent_doc_number] => 20180247681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND DATA READING METHOD [patent_app_type] => utility [patent_app_number] => 15/871101 [patent_app_country] => US [patent_app_date] => 2018-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871101 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/871101
Semiconductor memory device and data reading method Jan 14, 2018 Issued
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