Search

Toan K. Le

Examiner (ID: 18217)

Most Active Art Unit
2824
Art Unit(s)
2825, 2824, 3722
Total Applications
1303
Issued Applications
1255
Pending Applications
5
Abandoned Applications
46

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13349141 [patent_doc_number] => 20180226110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VARIATIONS OF PARAMETERS IN MULTIPLE LAYERS OF MEMORY [patent_app_type] => utility [patent_app_number] => 15/868280 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868280 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868280
Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory Jan 10, 2018 Issued
Array ( [id] => 13629283 [patent_doc_number] => 20180366194 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2018-12-20 [patent_title] => GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS [patent_app_type] => utility [patent_app_number] => 15/868234 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868234 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868234
Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations Jan 10, 2018 Issued
Array ( [id] => 13629283 [patent_doc_number] => 20180366194 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2018-12-20 [patent_title] => GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS [patent_app_type] => utility [patent_app_number] => 15/868234 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868234 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868234
Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations Jan 10, 2018 Issued
Array ( [id] => 14737887 [patent_doc_number] => 10388352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Parallel access techniques within memory sections through section independence [patent_app_type] => utility [patent_app_number] => 15/855643 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 11635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855643 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855643
Parallel access techniques within memory sections through section independence Dec 26, 2017 Issued
Array ( [id] => 14252089 [patent_doc_number] => 10276251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-30 [patent_title] => Partial memory die with masked verify [patent_app_type] => utility [patent_app_number] => 15/851139 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 12858 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15851139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/851139
Partial memory die with masked verify Dec 20, 2017 Issued
Array ( [id] => 14252083 [patent_doc_number] => 10276248 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-30 [patent_title] => Early ramp down of dummy word line voltage during read to suppress select gate transistor downshift [patent_app_type] => utility [patent_app_number] => 15/849019 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 38 [patent_no_of_words] => 18138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849019 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849019
Early ramp down of dummy word line voltage during read to suppress select gate transistor downshift Dec 19, 2017 Issued
Array ( [id] => 14493393 [patent_doc_number] => 10333501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Buffer circuit and device including the same [patent_app_type] => utility [patent_app_number] => 15/847523 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4824 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847523 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/847523
Buffer circuit and device including the same Dec 18, 2017 Issued
Array ( [id] => 13157699 [patent_doc_number] => 10095574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Apparatuses and methods for comparing a current representative of a number of failing memory cells [patent_app_type] => utility [patent_app_number] => 15/840610 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5468 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840610 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840610
Apparatuses and methods for comparing a current representative of a number of failing memory cells Dec 12, 2017 Issued
Array ( [id] => 12823075 [patent_doc_number] => 20180166197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SPIN ORBIT TORQUE GENERATING MATERIALS [patent_app_type] => utility [patent_app_number] => 15/836421 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836421 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/836421
Spin orbit torque generating materials Dec 7, 2017 Issued
Array ( [id] => 15185311 [patent_doc_number] => 20190363247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/470039 [patent_app_country] => US [patent_app_date] => 2017-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16470039 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/470039
Non-volatile memory Dec 5, 2017 Issued
Array ( [id] => 16323962 [patent_doc_number] => 10783932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Magnetic memory, semiconductor device, electronic device, and method of reading magnetic memory [patent_app_type] => utility [patent_app_number] => 16/486585 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13973 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16486585 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/486585
Magnetic memory, semiconductor device, electronic device, and method of reading magnetic memory Nov 30, 2017 Issued
Array ( [id] => 16447973 [patent_doc_number] => 10839904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Memory module for platform with non-volatile storage [patent_app_type] => utility [patent_app_number] => 16/467619 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16467619 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/467619
Memory module for platform with non-volatile storage Nov 19, 2017 Issued
Array ( [id] => 14919985 [patent_doc_number] => 10431319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Selectable trim settings on a memory device [patent_app_type] => utility [patent_app_number] => 15/802521 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5007 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802521 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802521
Selectable trim settings on a memory device Nov 2, 2017 Issued
Array ( [id] => 14706679 [patent_doc_number] => 10381097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Read mode tuning [patent_app_type] => utility [patent_app_number] => 15/799815 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799815
Read mode tuning Oct 30, 2017 Issued
Array ( [id] => 14011241 [patent_doc_number] => 10224095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Semiconductor device having multiport memory [patent_app_type] => utility [patent_app_number] => 15/795502 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 11275 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 538 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795502 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795502
Semiconductor device having multiport memory Oct 26, 2017 Issued
Array ( [id] => 15389021 [patent_doc_number] => 10535711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Memory devices and memory device forming methods [patent_app_type] => utility [patent_app_number] => 15/792585 [patent_app_country] => US [patent_app_date] => 2017-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 11101 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792585 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/792585
Memory devices and memory device forming methods Oct 23, 2017 Issued
Array ( [id] => 13242513 [patent_doc_number] => 10134463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Reconfigurable clocking architecture [patent_app_type] => utility [patent_app_number] => 15/727850 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8129 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727850 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727850
Reconfigurable clocking architecture Oct 8, 2017 Issued
Array ( [id] => 14858697 [patent_doc_number] => 10418082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Minimizing two-step and hard state transitions in multi-level STT-MRAM devices [patent_app_type] => utility [patent_app_number] => 15/724075 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4656 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724075 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724075
Minimizing two-step and hard state transitions in multi-level STT-MRAM devices Oct 2, 2017 Issued
Array ( [id] => 12919837 [patent_doc_number] => 20180198455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => INTEGRATED CIRCUIT HAVING A CLOCK DESKEW CIRCUIT THAT INCLUDES AN INJECTION-LOCKED OSCILLATOR [patent_app_type] => utility [patent_app_number] => 15/720401 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720401 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720401
Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator Sep 28, 2017 Issued
Array ( [id] => 13451331 [patent_doc_number] => 20180277208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => METHODS AND APPARATUS FOR PROGRAMMING BARRIER MODULATED MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 15/714463 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714463 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714463
METHODS AND APPARATUS FOR PROGRAMMING BARRIER MODULATED MEMORY CELLS Sep 24, 2017 Abandoned
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