Toan V. Tran

Array ( [id] => 4342812 [patent_doc_number] => 06333647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Sensor with dynamic latch' [patent_app_type] => 1 [patent_app_number] => 9/547066 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3180 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333647.pdf [firstpage_image] =>[orig_patent_app_number] => 547066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1472253 [patent_doc_number] => 06407604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Register and latch circuits' [patent_app_type] => B1 [patent_app_number] => 09/544786 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8726 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407604.pdf [firstpage_image] =>[orig_patent_app_number] => 09544786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4353423 [patent_doc_number] => 06285230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Input buffer circuit with adjustable delay via an external power voltage' [patent_app_type] => 1 [patent_app_number] => 9/544215 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 2821 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285230.pdf [firstpage_image] =>[orig_patent_app_number] => 544215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4339444 [patent_doc_number] => 06313685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Offset cancelled integrator' [patent_app_type] => 1 [patent_app_number] => 9/543181 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3512 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313685.pdf [firstpage_image] =>[orig_patent_app_number] => 543181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4387805 [patent_doc_number] => 06304121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Process strength indicator' [patent_app_type] => 1 [patent_app_number] => 9/543404 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6564 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304121.pdf [firstpage_image] =>[orig_patent_app_number] => 543404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4277658 [patent_doc_number] => 06307408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method and apparatus for powering down a line driver' [patent_app_type] => 1 [patent_app_number] => 9/543201 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3139 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307408.pdf [firstpage_image] =>[orig_patent_app_number] => 543201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416105 [patent_doc_number] => 06265923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Dual rail dynamic flip-flop with single evaluation path' [patent_app_type] => 1 [patent_app_number] => 9/543372 [patent_app_country] => US [patent_app_date] => 2000-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5170 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265923.pdf [firstpage_image] =>[orig_patent_app_number] => 543372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4412158 [patent_doc_number] => 06271690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Discriminator' [patent_app_type] => 1 [patent_app_number] => 9/534873 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 12568 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271690.pdf [firstpage_image] =>[orig_patent_app_number] => 534873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416295 [patent_doc_number] => 06229374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Variable gain amplifiers and methods having a logarithmic gain control function' [patent_app_type] => 1 [patent_app_number] => 9/534644 [patent_app_country] => US [patent_app_date] => 2000-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2928 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229374.pdf [firstpage_image] =>[orig_patent_app_number] => 534644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4412123 [patent_doc_number] => 06271687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Sense amplifier circuit' [patent_app_type] => 1 [patent_app_number] => 9/531530 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6689 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271687.pdf [firstpage_image] =>[orig_patent_app_number] => 531530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4312224 [patent_doc_number] => 06326818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Delta-sigma sample and hold' [patent_app_type] => 1 [patent_app_number] => 9/527554 [patent_app_country] => US [patent_app_date] => 2000-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1960 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326818.pdf [firstpage_image] =>[orig_patent_app_number] => 527554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4327210 [patent_doc_number] => 06331794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Phase leg with depletion-mode device' [patent_app_type] => 1 [patent_app_number] => 9/521487 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6154 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331794.pdf [firstpage_image] =>[orig_patent_app_number] => 521487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4277883 [patent_doc_number] => 06307422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Circuit configuration having single-electron components, a method for its operation and use of the method for addition of binary numbers' [patent_app_type] => 1 [patent_app_number] => 9/516658 [patent_app_country] => US [patent_app_date] => 2000-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7539 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307422.pdf [firstpage_image] =>[orig_patent_app_number] => 516658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1479192 [patent_doc_number] => 06344766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Voltage level converter circuit improved in operation reliability' [patent_app_type] => B1 [patent_app_number] => 09/515594 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13047 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344766.pdf [firstpage_image] =>[orig_patent_app_number] => 09515594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4304121 [patent_doc_number] => 06198331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Voltage level converter circuit improved in operation reliability' [patent_app_type] => 1 [patent_app_number] => 9/516212 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11944 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198331.pdf [firstpage_image] =>[orig_patent_app_number] => 516212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416061 [patent_doc_number] => 06229352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Power level detection circuit' [patent_app_type] => 1 [patent_app_number] => 9/513940 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3631 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229352.pdf [firstpage_image] =>[orig_patent_app_number] => 513940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1462233 [patent_doc_number] => 06392473 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Voltage protection and biasing circuit' [patent_app_type] => B1 [patent_app_number] => 09/481222 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2048 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392473.pdf [firstpage_image] =>[orig_patent_app_number] => 09481222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4365338 [patent_doc_number] => 06169431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Drive circuit for a controllable semiconductor component' [patent_app_type] => 1 [patent_app_number] => 9/477134 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4746 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169431.pdf [firstpage_image] =>[orig_patent_app_number] => 477134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4334069 [patent_doc_number] => 06329857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Apparatus, method and system for a logic arrangement having mutually exclusive outputs controlled by buffering cross-coupled devices' [patent_app_type] => 1 [patent_app_number] => 9/476157 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 16603 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329857.pdf [firstpage_image] =>[orig_patent_app_number] => 476157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4327191 [patent_doc_number] => 06331793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Apparatus, method and system for pulse passgate topologies' [patent_app_type] => 1 [patent_app_number] => 9/476285 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 16559 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331793.pdf [firstpage_image] =>[orig_patent_app_number] => 476285 [rel_patent_id] =>[rel_patent_doc_number] =>)